|
|
PDF MAX9602EUG Data sheet ( Hoja de datos )
| Número de pieza | MAX9602EUG | |
| Descripción | Dual ECL and Dual/Quad PECL / 500ps / Ultra-High-Speed Comparators | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX9602EUG (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
19-2409; Rev 1; 9/02
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
General Description
The MAX9600/MAX9601/MAX9602 ultra-high-speed com-
parators feature extremely low propagation delay
(500ps). These dual and quad comparators minimize
propagation delay skew (10ps) and are designed for low
propagation delay dispersion (30ps). These features
make them ideal for applications where high-fidelity track-
ing of narrow pulses and low timing dispersion is critical.
The differential input stage accepts a wide range of signals
in the common-mode range from (VEE + 3V) to (VCC - 2V).
The outputs are complementary digital signals, compatible
with ECL and PECL systems, and provide sufficient current
to directly drive transmission lines terminated in 50Ω.
The MAX9600/MAX9601 dual-channel ECL and dual-chan-
nel PECL output comparators incorporate latch enable
(LE_, LE_), and hysteresis (HYS_). The complementary
latch-enable control permits tracking, track-hold, or sample-
hold mode of operations. The latch enables can be driven
with standard ECL logic for MAX9600 and PECL logic for
MAX9601. The MAX9602 quad-channel PECL output
comparator is ideal for high-density packaging in limit-
ed board space.
The MAX9600/MAX9601 are available in 20-pin TSSOP
packages, and the MAX9602 is offered in a 24-pin
TSSOP package. The MAX9600/MAX9601/MAX9602
are specified for operation from -40°C to +85°C.
Applications
VLSI and High-Speed Memory ATE
High-Speed Instrumentation
Scope/Logic Analyzer Front Ends
High-Speed Triggering
Threshold and Peak Detection
Line Receiving/Signal Restoration
Features
o 500ps Propagation Delay
o 30ps Propagation Delay Dispersion
o 4Gbps Tracking Frequency
o -2.2V to +3V Input Range with +5V/-5.2V Supplies
o -1.2V to +4V Input Range with +6V/-4.2V Supplies
o Differential ECL Outputs (MAX9600)
o Differential PECL Outputs (MAX9601/MAX9602)
o Latch Enable (MAX9600/MAX9601)
o Adjustable Hysteresis (MAX9600/MAX9601)
Ordering Information
PART
MAX9600EUP
MAX9601EUP
MAX9602EUG
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 TSSOP
20 TSSOP
24 TSSOP
Selector Guide
PART
MAX9600EUP
PIN-PACKAGE
SELECTION
20 TSSOP
Dual ECL Output
Comparator with Latch
Enable and Hysteresis
MAX9601EUP 20 TSSOP
Dual PECL Output
Comparator with Latch
Enable and Hysteresis
MAX9602EUG 24 TSSOP
Quad PECL Output
Comparator
Pin Configurations appear at end of data sheet.
Functional Diagrams
VCC VEE GND
VCC VEE VCCO_
VCC VEE VCCO_
IN_+
IN_-
HYS_
RHYS_
1/2 MAX9600
Q_
ECL OUTPUT
Q_
RL RL
LE_ LE_
VT = -2V
IN_+
IN_-
HYS_
RHYS_
1/2 MAX9601
Q_ IN_+
PECL OUTPUT
Q_ IN_-
RL RL
LE_ LE_
VT = VCCO_ - 2V
1/4 MAX9602
Q_
PECL OUTPUT
Q_
RL RL
VT = VCCO_ - 2V
THE OPEN-EMITTER OUTPUTS REQUIRE EXTERNAL PULLDOWN RESISTORS (RL). USE RESISTORS IN THE RANGE OF 50Ω TO 75Ω CONNECTED TO VT.
CURRENT-CONTROLLED HYSTERESIS REQUIRES A SINGLE EXTERNAL RESISTOR (RHYS_) FROM HYS_ TO GND IN THE RANGE OF 10kΩ TO 35kΩ.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
Typical Operating Characteristics
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL = 5pF, GND = 0V,
RL = 50Ω to -2V (MAX9600), VCCO_ = 5V, RL = 50Ω to 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%,
TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PROPAGATION DELAY vs. INPUT OVERDRIVE
(VCC = 10mV TO 100mV)
530
520
510
500
490
480
470
10 20 30 40 50 60 70 80 90 100
INPUT OVERDRIVE (mV)
PROPAGATION DELAY vs. INPUT OVERDRIVE
(VOD = 0.1V TO 2V)
560
540
520
500
480
460
440
420
400
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
INPUT OVERDRIVE (V)
3500
3000
2500
2000
1500
1000
500
0
0
PROPAGATION DELAY
vs. SOURCE IMPEDANCE
100 200 300 400 500 600
SOURCE IMPEDANCE (Ω)
1500
1250
1000
750
500
250
0
0
PROPAGATION DELAY
vs. CAPACITIVE LOAD
5 10 15 20 25
CAPACITIVE LOAD (pF)
30
550
540
530
520
510
500
490
480
470
-50
PROPAGATION DELAY
vs. TEMPERATURE
-25 0 25 50 75
TEMPERATURE (°C)
100
PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
530
520
510
500
490
480
470
-3
-2 -1 0 1 2
COMMON-MODE VOLTAGE (V)
3
_______________________________________________________________________________________ 5
5 Page 
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
Timing Information (MAX9600/MAX9601)
The timing diagram (Figure 1) illustrates the operation
of a comparator with latch enable. The top line of the
diagram illustrates a latch-enable pulse. Initially, the
latch-enable input (LE, LE_) is differentially high, which
places the comparator in latch mode. When the input
signal (IN_+, IN_-) switches from low to high, the output
(Q_, Q_) remains latched to the previous low state.
When the latch-enable input goes differentially low,
starting the compare function, the output responds to
the input and transitions to high after a time (tLPD). The
leading edges of the subsequent input signal switch
the comparator after time interval tPD+ or tPD- (depend-
ing on the direction of the input transitions) until a high
latch-enable pulse places the device in latch mode
again. The input signal must occur at minimum time
(tLS) before the latch rising edge, and must maintain its
state for at least tLH after the rising edge. A minimum
latch-pulse width (tLPW) of 250ps (typ) is needed for
proper latch operation.
ECL/PCL
The MAX9600/MAX9601/MAX9602 outputs are emitter
followers that require external resistive connections to a
voltage source (VT) more negative than the lowest VOL
for proper static and dynamic operation. When properly
terminated, the outputs provide appropriate levels, VOL
or VOH, for ECL (MAX9600) or PECL (MAX9601/
MAX9602). Output-current polarity always sinks into the
termination scheme during proper operation.
ECL-output signal levels are referenced to GND, and
PECL-output signals are referenced to VCCO_.
Chip Information
MAX9600 TRANSISTOR COUNT: 558
MAX9601 TRANSISTOR COUNT: 600
MAX9602 TRANSISTOR COUNT: 608
PROCESS: Bipolar
Pin Configurations
TOP VIEW
QA 1
QA 2
GND 3
LEA 4
LEA 5
VEE 6
VCC 7
HYSA 8
INA- 9
INA+ 10
MAX9600
20 QB
19 QB
18 GND
17 LEB
16 LEB
15 VEE
14 VCC
13 HYSB
12 INB-
11 INB+
TSSOP-20
QA 1
QA 2
VCCOA 3
LEA 4
LEA 5
VEE 6
VCC 7
HYSA 8
INA- 9
INA+ 10
MAX9601
20 QB
19 QB
18 VCCOB
17 LEB
16 LEB
15 VEE
14 VCC
13 HYSB
12 INB-
11 INB+
TSSOP-20
INA+ 1
INA- 2
VEE 3
INB+ 4
INB- 5
VCC 6
INC+ 7
INC- 8
VEE 9
IND+ 10
IND- 11
VCC 12
MAX9602
24 VCCOA
23 QA
22 QA
21 VCCOB
20 QB
19 QB
18 VCCOC
17 QC
16 QC
15 VCCOD
14 QD
13 QD
TSSOP-24
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX9602EUG.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX9602EUG | Dual ECL and Dual/Quad PECL / 500ps / Ultra-High-Speed Comparators | Maxim Integrated |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |