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PDF MAX9485 Data sheet ( Hoja de datos )
| Número de pieza | MAX9485 | |
| Descripción | Programmable Audio Clock Generator | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-3315; Rev 0; 7/04
ProgrammableEVFAOLLULAOTWIOSNDKAITTAMSAHNEUEATL Audio Clock Generator
General Description
The MAX9485 programmable multiple-output clock
generator provides a cost-efficient solution for MPEG-2
audio systems such as DVD players, DVD drives for
multimedia PCs, digital HDTV systems, home entertain-
ment centers, and set-top boxes.
The MAX9485 accepts an input reference frequency of
27MHz from a crystal or system reference clock. The
device provides two buffered clock outputs of 256, 384,
or 768 times the chosen sampling frequency (fS) select-
ed through an I2C™ interface or hardwired inputs.
Sampling frequencies of 12kHz, 32kHz, 44.1kHz,
48kHz, 64kHz, 88.2kHz, or 96kHz are available. The
MAX9485 also offers a buffered 27MHz output and an
integrated voltage-controlled oscillator (VCXO) that is
tuned by a DC voltage generated from the MPEG
processor. The use of VCXO allows the audio system
clock to lock with the overall system clock.
The MAX9485 features the lowest jitter in its class, guar-
anteeing excellent dynamic performance with audio
ADCs and DACs in an MPEG-2 audio system. The
device operates with a 3.3V supply and is specified over
the -40°C to +85°C extended temperature range. The
MAX9485 is offered in 6.5mm x 4.4mm 20-pin TSSOP
and 4mm x 4mm 20-pin thin QFN packages.
Applications
Digital TVs
DVD Players
Set-Top Boxes
HDTVs
Home Entertainment
Centers
Features
♦ 27MHz Crystal with ±30ppm Frequency Reference
♦ Two Buffered Output Ports with Multiple Audio
Clocks: 256, 384, or 768 Times fS
♦ Supports Standard and Double Sampling Rates
(12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz,
and 96kHz)
♦ I2C Interface or Hardwired Output Clock Selection
♦ Separate Output Clock Enable
♦ Low Jitter Typical 21ps (RMS at 73.728MHz)
♦ No External Components for PLL
♦ Integrated VCXO with ±200ppm Tuning Range
♦ Small Footprint, Thin QFN Package, 4mm x 4mm
Ordering Information
PART
MAX9485ETP
MAX9485EUP
*EP = Exposed pad.
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 Thin QFN-EP*
20 TSSOP
I2C is a trademark of Philips Corp.
Purchase of I2C components of Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these com-
ponents in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
Pin Configurations
TOP VIEW
VDD_P 1
GND_P 2
TUN 3
X1 4
X2 5
VDD 6
SCL/FS0 7
SDA/FS1 8
FS2 9
GND 10
MAX9485
20 SAO2
19 SAO1
18 MCLK
17 VDD
16 CLK_OUT2
15 GND
14 CLK_OUT1
13 MODE
12 RST
11 GND
TSSOP
TUN 1
X1 2
X2 3
VDD
SCL/FS0
4
5
MAX9485
EXPOSED PAD
(GROUND)
15 VDD
14 CLK_OUT2
13 GND
12 CLK_OUT1
11 MODE
THIN QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Programmable Audio Clock Generator
(VDD = VDD_P = 3.3V, TA = +25°C.)
Typical Operating Characteristics
SUPPLY CURRENT
vs. LOAD CAPACITANCE
50
VTUN = 1.5V
fCLK_OUT = 73.728MHz
40
SUPPLY CURRENT vs. VTUN
50
CL = 20pF
fCLK_OUT = 73.728MHz
40
SUPPLY CURRENT
vs. OUTPUT FREQUENCY
50
VTUN = 1.5V
CL = 20pF
40
30 30 30
20 20 20
10 10 10
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
0
OUTPUT CLOCK RISE/FALL TIME
vs. LOAD CAPACITANCE
3.0
VTUN = 1.5V
2.5 fCLK_OUT = 73.728MHz
2.0
0.5 1.0 1.5 2.0 2.5 3.0
VTUN (V)
0
0 10 20 30 40 50 60 70 80
OUTPUT FREQUENCY (MHz)
MCLK PULLING RANGE
vs. VTUN
300
CX1 = CX2 = 4.7pF
200
CX1 = CX2 = 5.6pF
100
1.5
1.0 RISE TIME (tR)
0.5 FALL TIME (tF)
0
-100 CX1 = CX2 = 6.8pF
-200
0
0 4 8 12 16
LOAD CAPACITANCE (pF)
MCLK PERIOD JITTER
vs. OUTPUT FREQUENCY
50
VTUN = 1.5V
CL = 15pF
40
20
-300
0
0.5 1.0 1.5 2.0 2.5 3.0
VTUN (V)
CLK_OUT PERIOD JITTER
vs. OUTPUT FREQUENCY
500
VTUN = 1.5V
CL = 15pF
400
30 300
20 200
10 100
0
0 10 20 30 40 50 60 70 80
OUTPUT FREQUENCY (MHz)
0
0 10 20 30 40 50 60 70 80
OUTPUT FREQUENCY (MHz)
_______________________________________________________________________________________ 5
5 Page 
Programmable Audio Clock Generator
Table 13. Frequency Scaling Factors
C3 C2 OUTPUT SCALING FACTOR
00
256
01
384
10
768
11
Reserved
Table 14. Sampling Frequency Selection
C1 C0 SAMPLING FREQUENCY (kHz)
00
12
01
32
10
44.1
11
48
Note: (C1, C0) = (0, 0) and C4 = 1 (double) is not a proper selec-
tion. However, when set, it selects 12kHz sampling frequency.
SDA
SCL S
START
CONDITION
Figure 5. Start and Stop Conditions
P
STOP
CONDITION
MASTER-WRITE DATA STRUCTURE
S
SLAVE ADDRESS
7 BITS
R/W A
DATA
8 BITS
AP
SDA line operates as both an input and an open-drain
output. A pullup resistor, typically 4.7kΩ, is required on
SDA. The SCL line operates only as an input. A pullup
resistor, typically 4.7kΩ, is required on SCL if there are
multiple masters on the 2-wire bus, or if the master in a
single-master system has an open-drain SCL output.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
idle. The active master signals the beginning of a trans-
mission with a START (S) condition by transitioning
SDA from high to low while SCL is high. After communi-
cation, the MAX9485 issues a STOP (P) condition by
transitioning SDA from low to high while SCL is high,
freeing the bus for another transmission (Figure 5). If a
START or STOP occurs while a bus transaction is in
progress, then it terminates the transaction.
Data Transfer and Acknowledge
Following the START condition, each SCL clock pulse
transfers 1 bit. For the MAX9485 interface, between a
START and a STOP, 18 bits are transferred on the
2-wire bus. The first 7 bits are for the device address.
Bit 8 indicates the writing (low) or reading (high) opera-
tion (R/W). Bit 9 is the ACK for the address and opera-
tion type. Bits 10 though 17 form the data byte. Bit 18 is
the ACK for the data byte. The master always transfers
MASTER-READ DATA STRUCTURE
S
SLAVE ADDRESS
7 BITS
R/W A
DATA
8 BITS
A = ACK; A = 0: ACKNOWLEDGE, A = 1: NOT ACKNOWLEDGE
S = START CONDITION
P = STOP CONDITION
MASTER TRANSFERS TO SLAVE
AP
SLAVE TRANSFERS TO MASTER
Figure 6. Serial Interface Data Structure
the first 8 bits (address + R/W). The slave (MAX9485)
can receive the data byte from the bus or transfer it to
the bus from the internal register. The ACK bits are
transmitted by the address or data recipient. A low
ACK bit indicates a successful transfer (Acknowledge),
a high ACK bit indicates an unsuccessful transfer (Not
Acknowledge). Figure 6 shows the structure of the data
transfer. During a write operation, if more synchronous
data is transferred, it overwrites the data in the register.
During a read operation, if more clocks are reset on
SCL, the SDA continues to respond to the register data.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX9485.PDF ] | |
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