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PDF MAX9374EKA-T Data sheet ( Hoja de datos )
| Número de pieza | MAX9374EKA-T | |
| Descripción | Differential LVPECL-to-LVDS Translators | |
| Fabricantes | Maxim Integrated | |
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19-2326; Rev 0; 1/02
Differential LVPECL-to-LVDS Translators
General Description
The MAX9374 and MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators and are designed for tele-
com applications. They feature 250ps propagation
delay. The differential output conforms to the ANSI
TIA/EIA-644 LVDS standard. The inputs are biased with
internal resistors such that the output is differential low
when inputs are open. An on-chip VBB reference output
is available for single-ended operation.
The MAX9374 is designed for low-voltage operation
from a 2.375V to 2.625V power supply for use in 2.5V
systems. The MAX9374A is designed for 3.0V to 3.6V
operation in systems with a nominal 3.3V supply. Both
devices are offered in industry-standard 8-pin SOT23
and SO packages.
Features
o Guaranteed 2.0GHz Operating Frequency
o 250ps (typ) Propagation Delay
o 1.0ps RMS Jitter (typ)
o 2.375V to 2.625V Low-Voltage Supply Range
(MAX9374)
o On-Chip VBB Reference for Single-Ended Input
o Output Low for Open Inputs
o Output Conforms to ANSI TIA/EIA-644 LVDS
Standard
o ESD Protection >2.0kV (Human Body Model)
o Available in Small 8-Pin SOT23 Package
Applications
Precision Clock Buffer
Low-Jitter Data Repeater
Central Office Clock Distribution
DSLAM/DLC
Base Station
Mass Storage
Ordering Information
PART
MAX9374EKA-T
MAX9374ESA
MAX9374AEKA-T
MAX9374AESA
TEMP
RANGE
PIN-
PACKAGE
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SO
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SO
TOP
MARK
AAKU
—
AAKV
—
Pin Configurations/Functional Diagrams appear at end of
data sheet.
Typical Application Circuit
MAX9374/MAX9374A
DQ
LVPECL
INPUT
DQ
Z0 = 50Ω
100Ω
Z0 = 50Ω
LVDS RECEIVER
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Differential LVPECL-to-LVDS Translators
PIN
SOT23 SO
14
25
33
42
58
67
76
81
Pin Description
NAME
FUNCTION
VBB
GND
D
D
VCC
Q
Q
N.C.
Reference Output Voltage. Connect to the inverting or noninverting data input to provide a reference
for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise,
leave it open.
Ground. Provide a low-impedance connection to the ground plane.
Inverted LVPECL Data Input. 36.5kΩ pullup to VCC and 75kΩ pulldown to GND.
Noninverted LVPECL Data Input. 75kΩ pullup to VCC and 75kΩ pulldown to GND.
Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverted LVDS Output. Typically terminate with 100Ω to Q.
Inverted LVDS Output. Typically terminate with 100Ω to Q.
No Connection. Not internally connected.
D
VIHD - VILD
D
tPLH_
tPHL_
VIHD
VILD
Q VOH
VOD VOS
Q VOL
80%
0 (DIFFERENTIAL)
(Q) - (Q)
20%
tR
Figure 1. MAX9374/MAX9374A Timing Diagram
80%
0 (DIFFERENTIAL)
20%
tF
_______________________________________________________________________________________ 5
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