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PDF MAX9157EGJ Data sheet ( Hoja de datos )
| Número de pieza | MAX9157EGJ | |
| Descripción | Quad Bus LVDS Transceiver | |
| Fabricantes | Maxim Integrated | |
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19-2287; Rev 0; 1/02
Quad Bus LVDS Transceiver
General Description
The MAX9157 is a quad bus LVDS (BLVDS) transceiver
for heavily loaded, half-duplex multipoint buses. Small
32-pin QFN and TQFP packages and flow-through
pinouts allow the transceiver to be placed near the con-
nector for the shortest possible stub length. The
MAX9157 drives LVDS levels into a 27Ω load (double
terminated, heavily loaded LVDS bus) at up to
200Mbps. An input fail-safe circuit ensures the receiver
output is high when the differential inputs are open, or
undriven and shorted, or undriven and terminated. The
MAX9157 differential inputs feature 52mV hysteresis for
greater immunity to bus noise and reflections. The
MAX9157 operates from a single 3.3V supply, consum-
ing 80.9mA supply current with drivers enabled, and
22.7mA with drivers disabled.
The MAX9157’s high-impedance I/Os (except for
receiver outputs) when VCC = 0 or open, combined
with glitch-free power-up and power-down, allow hot
swapping of cards in multicard bus systems; 7.2pF
(max) BLVDS I/O capacitances minimize bus loading.
The MAX9157 is offered in 5mm ✕ 5mm 32-pin QFN and
TQFP packages. The MAX9157 is fully specified for the
-40°C to +85°C extended temperature range. Refer to
the MAX9129 data sheet for a quad BLVDS driver, ideal
for dual multipoint full-duplex buses.
Applications
Add/Drop Muxes
Digital Cross-Connects
Network
Switches/Routers
Cellular Phone Base
Stations
DSLAMs
Multipoint Buses
Features
o 32-TQFP and Space-Saving 32-QFN Packages
o 52mV LVDS Input Hysteresis
o 1ns (min) Transition Time (0% to 100%) Minimizes
Reflections
o Guaranteed 7.2pF (max) Bus Load Capacitance
o Glitch-Free Power-Up and Power-Down
o Hot-Swappable, High-Impedance I/O with VCC = 0
or Open
o Guaranteed 200Mbps Driver Data Rate
o Fail-Safe Circuit
o Flow-Through Pinout
PART
MAX9157EGJ
MAX9157EHJ
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 QFN (5mm ✕ 5mm)
32 TQFP (5mm ✕ 5mm)
Pin Configurations appear at end of data sheet.
Functional Diagram appears at end of data sheet.
MAX9157
CARD 1
MAX9157
CARD 15
Typical Operating Circuit
MAX9157
CARD 16
1in CARD
SPACING
Rt = 54Ω
Rt = 54Ω
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Quad Bus LVDS Transceiver
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL = 27Ω ±1%, differential input voltage |VID| = 0.2V to VCC, input frequency to LVDS inputs = 85MHz, input fre-
quency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times. Differential input
voltage transition time = 1ns (20% to 80%). Input common-mode voltage VCM = 1.2V to 1.8V, DE_ = high, RE_ = low, TA = -40°C to
+85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25°C.) (Notes 3 and 5)
PARAMETER
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
tTHL DE_ = low, Figures 7, 8; CL = 15pF
0.7 1.2 1.8
ns
tPHZ
DE_ = low, RL = 500Ω, CL MAX9157EGJ
= 15pF, Figures 9, 10
MAX9157EHJ
6.74 8
6.82 8
ns
tPLZ
DE_
=
low,
RL
=
500Ω,
C
L
= 15pF, Figures 9, 10
MAX9157EGJ
MAX9157EHJ
6.49 8
6.79 8
ns
tPZH
DE_
=
low,
RL
=
500Ω,
C
L
= 15pF, Figures 9, 10
MAX9157EGJ
MAX9157EHJ
4.67 7
4.57 7
ns
tPZL
DE_
=
low,
RL
=
500Ω,
C
L
= 15pF, Figures 9, 10
MAX9157EGJ
MAX9157EHJ
5.43 7
4.71 7
ns
Maximum Operating Frequency
(Note 10)
fMAX
DE_ = low, C = 15pF
L
85 MHz
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VHYST, VOD, and ∆VOD.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: Guaranteed by design and characterization.
Note 4: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 5: CL includes scope probe and test jig capacitance.
Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |.
Note 7: tCCSK is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the
same part.
Note 8: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
the same VCC and within 5°C of each other.
Note 9: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
Note 10: Meets data sheet specifications while operating at minimum fMAX rating.
Typical Operating Characteristics
(VCC = 3.3V, RL = 27Ω, driver CL = 10pF, receiver CL = 15pF, |VID| = 200mV, VCM = 1.2V, fIN = 20MHz, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. FREQUENCY
105
FOUR CHANNELS
DRIVEN
100
95 VCC = 3.6V
90
VCC = 3.3V
85
80
75
0.01
VCC = 3.0V
0.1 1
10 100
FREQUENCY (MHz)
1000
DIFFERENTIAL OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
0.405
0.404
0.403
0.402
0.401
0.400
3.0
3.1 3.2 3.3 3.4 3.5
SUPPLY VOLTAGE (V)
3.6
DIFFERENTIAL OUTPUT VOLTAGE
vs. OUTPUT LOAD
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
15 45 75 105 135
OUTPUT LOAD (Ω)
_______________________________________________________________________________________ 5
5 Page 
Quad Bus LVDS Transceiver
DIN_
RIN_-
RIN_+
50%
tPLHD
0 DIFFERENTIAL
VCC
50%
tPHLD
0
VOH
0
VOL
VOD
20%
80% 80%
0
VOD = (VDO_+/RIN_+ - VDO_-/RIN_-)
0
20%
tTLH tTHL
Figure 4. Driver Propagation Delay and Transition Time
Waveforms
VCC
GND
GENERATOR
50Ω
DIN_
DE_
1/4 MAX9157
CL
DO_+/RIN_+
RL/2
+1.2V
RL/2
DO_-/RIN_-
CL
Figure 5. Driver High-Impedance Delay Test Circuit
DE_
D0_+/RIN_+ WHEN DIN_ = VCC
DO_-/RIN_- WHEN DIN_ = 0
50%
tPHZ
50%
DO_+/RIN_+ WHEN DIN_ = 0
DO_-/RIN_- WHEN DIN_ = VCC
Figure 6. Driver High-Impedance Delay Waveform
50%
tPLZ
50%
tPZH
50%
50%
tPZL
VCC
0
VOH
1.2V
1.2V
VOL
PULSE
GENERATOR
DO_+/RIN_+
DO_-/RIN_-
RO_
CL
50Ω*
50Ω*
RECEIVER ENABLED
1/4 MAX9157
*50Ω REQUIRED FOR PULSE GENERATOR TERMINATION.
Figure 7. Receiver Transition Time and Propagation Delay Test Circuit
______________________________________________________________________________________ 11
11 Page | ||
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| PDF Descargar | [ Datasheet MAX9157EGJ.PDF ] | |
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