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PDF SDA9361 Data sheet ( Hoja de datos )
| Número de pieza | SDA9361 | |
| Descripción | DDC-PLUS-Deflection Controller | |
| Fabricantes | Siemens | |
| Logotipo |  |
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ICs for Consumer Electronics
DDC-PLUS-Deflection Controller
SDA 9361
Data Sheet 1998-02-01
1 page  
DDC-PLUS-Deflection Controller
SDA 9361
MOS
1 Overview
1.1 Features
• Deflection - Protection - 16:9 / 4:3
• No external clock needed
• Φ1 PLL and Φ2 PLL on chip
• Ι2C-Bus alignment of all deflection parameters
• All EW-, V- and H- functions
P-MQFP-44-2
• PW EHT compensation
• PH EHT compensation
• Compensation of H-phase deviation (e.g. caused by white bar)
• Upper/lower EW-corner correction separately adjustable
• V-angle correction: Vertical frequent linear modulation of H-phase
• V-bow correction: Vertical frequent parabolic modulation of H-phase
• Three reduced V-scan modes (75 %, 66 %, 50 % V-size) adjustable by only 2 Bits
• H-frequent PWM output signal for general purpose
• H- and V-blanking time adjustable
• Partial overscan adjustable to hide the cut off control measuring lines in the
reducedscan modes
• Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different
letterbox formats without annoying overscan
• Control signal SCAN as reference for vertical positioning of OSD, PIP etc.
• Vertical noise reduction with memory
• Standard and doubled line frequencies for NTSC and PAL, MUSE standard,
ATV standard, HDTV standard
• Self adaptation of V-frequency/number of lines per field between 192 and 680 for each
possible line frequency
• Protection against EHT run away (X-rays protection)
Type
SDA 9361
Semiconductor Group
Ordering Code
Q67107-H5167-A703
5
Package
P-MQFP-44-2
1998-02-01
5 Page 
SDA 9361
VPROT:
Vertical saw-tooth voltage
Vi < V1 in first half of V-period or
Vi > V2 in second half: HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (Vb), H-
blanking HBL (VHBL) and selectable V-blanking (control bit SSC). The phase and width
of the H-blanking period can be varied by Ι2C Bus. For the timing following settings are
possible:
BD = 1
BD = 0, BSE = 0 (default value)
BD = 0, BSE = 1(alignment range)
SSC = 0
SSC = 1
: tBL = 0
: tHBL = tf (H-flyback time)
: tHBL = (4 * H-blanking-time + 1) / CLL
: tDBL = (H-shift + 4 * H-blanking-phase
-2 * H-blanking-time + 43) / CLL
: tBL = tVBL during V-blanking period
: tBL is always tHBL
Input Signal
HSYNC
VOH
VOHBL
VOL
t DB
t DBL
tB
t BL
UED10260
Figure 3
BG-pulse width tB
Delay to HSYNC tDB
Semiconductor Group
54 / CLL
if CLEXT = L-level: (76-4 * Internal-H-sync-phase) / CLL
if CLEXT = H-level: (38-4 * Internal-H-sync-phase) / CLL
11 1998-02-01
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet SDA9361.PDF ] | |
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