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PDF MCP41010 Data sheet ( Hoja de datos )
| Número de pieza | MCP41010 | |
| Descripción | Single/Dual Digital Potentiometer with SPI Interface | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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M
MCP41XXX/42XXX
Single/Dual Digital Potentiometer with SPI™ Interface
Features
• 256 taps for each potentiometer
• Potentiometer values for 10 kΩ, 50 kΩ and
100 kΩ
• Single and dual versions
• SPI™ serial interface (mode 0,0 and 1,1)
• ±1 LSB max INL & DNL
• Low power CMOS technology
• 1 µA maximum supply current in static operation
• Multiple devices can be daisy-chained together
(MCP42XXX only)
• Shutdown feature open circuits of all resistors for
maximum power savings
• Hardware shutdown pin available on MCP42XXX
only
• Single supply operation (2.7V - 5.5V)
• Industrial temperature range: -40°C to +85°C
• Extended temperature range: -40°C to +125°C
Block Diagram
VDD
VSS
Control
Logic
RS SHDN
Wiper
Register
PB0
Resistor
Array 0
PA0
PW0
CS
SI
SCK
16-Bit
Shift
Register
Wiper Resistor
Register Array 1*
S0
PB1
PA1
PW1
*Potentiometer P1 is only available on the dual
MCP42XXX version.
Description
The MCP41XXX and MCP42XXX devices are 256-
position, digital potentiometers available in 10 kΩ,
50 kΩ and 100 kΩ resistance versions. The
MCP41XXX is a single-channel device and is offered in
an 8-pin PDIP or SOIC package. The MCP42XXX con-
tains two independent channels in a 14-pin PDIP, SOIC
or TSSOP package. The wiper position of the
MCP41XXX/42XXX varies linearly and is controlled via
an industry-standard SPI interface. The devices con-
sume <1 µA during static operation. A software shut-
down feature is provided that disconnects the “A”
terminal from the resistor stack and simultaneously con-
nects the wiper to the “B” terminal. In addition, the dual
MCP42XXX has a SHDN pin that performs the same
function in hardware. During shutdown mode, the con-
tents of the wiper register can be changed and the
potentiometer returns from shutdown to the new value.
The wiper is reset to the mid-scale position (80h) upon
power-up. The RS (reset) pin implements a hardware
reset and also returns the wiper to mid-scale. The
MCP42XXX SPI interface includes both the SI and SO
pins, allowing daisy-chaining of multiple devices. Chan-
nel-to-channel resistance matching on the MCP42XXX
varies by less than 1%. These devices operate from a
single 2.7 - 5.5V supply and are specified over the
extended and industrial temperature ranges.
Package Types
PDIP/SOIC
CS
SCK
SI
VSS
1
2
3
4
8 VDD
7 PB0
6 PW0
5 PA0
PDIP/SOIC/TSSOP
CS
SCK
SI
VSS
PB1
PW1
PA1
1
2
3
4
5
6
7
14 VDD
13 SO
12 SHDN
11 RS
10 PB0
9 PW0
8 PA0
2003 Microchip Technology Inc.
DS11195C-page 1
1 page  
MCP41XXX/42XXX
Absolute Maximum Ratings †
VDD...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +1.0V
Storage temperature .....................................-60°C to +150°C
Ambient temp. with power applied ................-60°C to +125°C
ESD protection on all pins ..................................................≥ 2 kV
† Notice: Stresses above those listed under “maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC TIMING CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C.
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Clock Frequency
FCLK — — 10 MHz VDD = 5V (Note 1)
Clock High Time
tHI 40 — — ns
Clock Low Time
tLO 40 — — ns
CS Fall to First Rising CLK Edge
tCSSR 40 — — ns
Data Input Setup Time
tSU 40 — — ns
Data Input Hold Time
tHD 10 — — ns
SCK Fall to SO Valid Propagation Delay
tDO
— 80 ns CL = 30 pF (Note 2)
SCK Rise to CS Rise Hold Time
tCHS 30 — — ns
SCK Rise to CS Fall Delay
tCS0 10 — — ns
CS Rise to CLK Rise Hold
tCS1
100 —
—
ns
CS High Time
tCSH 40 — — ns
Reset Pulse Width
tRS 150 — — ns Note 2
RS Rising to CS Falling Delay Time
tRSCS 150 — — ns Note 2
CS rising to RS or SHDN falling delay time
tSE 40 — — ns Note 3
CS low time
tCSL
100 —
—
ns Note 3
Shutdown Pulse Width
tSH 150 — — ns Note 3
Note 1:
2:
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay
time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI =
40 ns, tDO = 80 ns and tSU = 40 ns.
Applies only to the MCP42XXX devices.
3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.
2003 Microchip Technology Inc.
DS11195C-page 5
5 Page 
2.1 Parametric Test Circuits
V+ = VDD
A 1LSB = V+/256
V+
W
B
DUT
+
-
VMEAS*
*Assume infinite input impedance
FIGURE 2-25:
Potentiometer Divider Non-
Linearity Error Test Circuit (DNL, INL).
No Connection
A
BW
DUT
IW
+
-
VMEAS*
*Assume infinite input impedance
FIGURE 2-26:
Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
DUT
A
W
B ISW
Rsw = 0.1V
Isw
Code = 00h
+
- 0.1V
VSS = 0 to VDD
FIGURE 2-27:
Circuit.
Wiper Resistance Test
MCP41XXX/42XXX
VA
VDD A
V+
BW
DUT
+
-
VMEAS*
V+ = VDD ± 10%
PSRR (dB) = 20LOG (∆∆VVMDDEAS)
PSS (%/%) = ∆VDD
∆VMEAS
*Assume infinite input impedance
FIGURE 2-28:
Power Supply Sensitivity
Test Circuit (PSS, PSRR).
VIN ~
OFFSET
GND
A
W
DUT
B
2.5V DC
+5V
+
-
VOUT
FIGURE 2-29:
Circuit.
Gain vs. Frequency Test
~VIN
A DUT B
+5V
2.5V DC
Offset
- VOUT
+ MCP601
FIGURE 2-30:
Capacitance Test Circuit.
2003 Microchip Technology Inc.
DS11195C-page 11
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet MCP41010.PDF ] | |
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