|
|
PDF MCM67M618B Data sheet ( Hoja de datos )
| Número de pieza | MCM67M618B | |
| Descripción | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MCM67M618B (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM67M618B/D
Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
MCM67M618B
The MCM67M618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC™ microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology. The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sig-
nals, except output enable (G), are clock (K) controlled through posi-
DQ9
DQ10
tive–edge–triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or
VCC
VSS
transfer start cache controller (TSC) input pins. Subsequent burst
DQ11
addresses are generated internally by the MCM67M618B (burst
DQ12
sequence imitates that of the MC68040) and controlled by the burst
address advance (BAA) input pin. The following pages provide more
detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
signals.
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
Dual write enables (LW and UW) are provided to allow individually
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory.
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/10/12 ns Max
• Byte Writeable via Dual Write Strobes
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• TSP, TSC, and BAA Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• High Board Density 52–PLCC Package
• 3.3 V I/O Compatible
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
7 6 5 4 3 2 1 52 51 50 49 48 47
8 46
9 45
10 44
11 43
12 42
13 41
14 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
BAA . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
TSP, TSC . . . . . . . . . . . . . . . . Transfer Start
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be con-
nected for proper operation of the device.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
7/15/97
©MMOoTtoOrolRa,OIncL.A19F97AST SRAM
MCM67M618B
1
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 3, and 4)
MCM67M618B–9 MCM67M618B–10 MCM67M618B–12
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Cycle Time
tKHKH
15
— 16.6 —
20
— ns
Clock Access Time
tKHQV
—
9
— 10 — 12 ns 5
Output Enable to Output Valid
tGLQV
—
5
—
5
—
6 ns
Clock High to Output Active
tKHQX1
6
—
6
—
6
— ns
Clock High to Output Change
tKHQX2
3
—
3
—
3
— ns
Output Enable to Output Active
tGLQX
0
—
0
—
0
— ns
Output Disable to Q High–Z
tGHQZ
—
6
—
7
—
7 ns 6
Clock High to Q High–Z
tKHQZ
3
6
3
7
3
7 ns 6
Clock High Pulse Width
tKHKL
5
—
5
—
6
— ns
Clock Low Pulse Width
tKLKH
5
—
5
—
6
— ns
Setup Times:
Address
tAVKH
2.5
—
2.5
—
2.5
— ns 7
Address Status tTSVKH
Data In tDVKH
Write tWVKH
Address Advance tBAVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
0.5
— ns 7
Address Status tKHTSX
Data In tKHDX
Write tKHWX
Address Advance tKHBAX
Chip Enable tKHEX
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
6. Transition is measured ± 500 mV from steady-state voltage. This parameter is sampled rather than 100% tested. At any given voltage and
temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges
of K when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V
Figure 1.Test Load
MOTOROLA FAST SRAM
MCM67M618B
5
5 Page 
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
–N–
Y BRK
D
B 0.007 (0.18) M T L–M S N S
U 0.007 (0.18) M T L–M S N S
Z
–L– –M–
W
D
52 1
V
X
VIEW D–D
G1
0.010 (0.25) S T L–M S N S
A 0.007 (0.18) M T L–M S N S
Z
R 0.007 (0.18) M T L–M S N S
C
G
E
J
VIEW S
0.004 (0.100)
–T– SEATING
PLANE
G1
0.010 (0.25) S T L–M S N S
H 0.007 (0.18) M T L–M S N S
K1
KF
VIEW S
0.007 (0.18) M T L–M S N S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.785 0.795 19.94 20.19
B 0.785 0.795 19.94 20.19
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC
1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 ––– 0.51 –––
K 0.025 ––– 0.64 –––
R 0.750 0.756 19.05 19.20
U 0.750 0.756 19.05 19.20
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y ––– 0.020 ––– 0.50
Z 2_ 10_ 2_ 10_
G1 0.710 0.730 18.04 18.54
K1 0.040 ––– 1.02 –––
MOTOROLA FAST SRAM
MCM67M618B
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MCM67M618B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MCM67M618 | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| MCM67M618A | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| MCM67M618B | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |