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PDF MF10CCN Data sheet ( Hoja de datos )

Número de pieza MF10CCN
Descripción Universal Monolithic Dual Switched Capacitor Filter
Fabricantes National 
Logotipo National Logotipo



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December 1994
MF10
Universal Monolithic Dual
Switched Capacitor Filter
General Description
The MF10 consists of 2 independent and extremely easy to
use general purpose CMOS active filter building blocks
Each block together with an external clock and 3 to 4 resis-
tors can produce various 2nd order functions Each building
block has 3 output pins One of the outputs can be config-
ured to perform either an allpass highpass or a notch func-
tion the remaining 2 output pins perform lowpass and band-
pass functions The center frequency of the lowpass and
bandpass 2nd order functions can be either directly depen-
dent on the clock frequency or they can depend on both
clock frequency and external resistor ratios The center fre-
quency of the notch and allpass functions is directly depen-
dent on the clock frequency while the highpass center fre-
quency depends on both resistor ratio and clock Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10 higher than 4th order
functions can be obtained by cascading MF10 packages
Any of the classical filter configurations (such as Butter-
worth Bessel Cauer and Chebyshev) can be formed
For pin-compatible device with improved performance refer
to LMF100 datasheet
Features
Y Easy to use
Y Clock to center frequency ratio accuracy g0 6%
Y Filter cutoff frequency stability directly dependent on
external clock quality
Y Low sensitivity to external component variation
Y Separate highpass (or notch or allpass) bandpass low-
pass outputs
Y fO c Q range up to 200 kHz
Y Operation up to 30 kHz
Y 20-pin 0 3 wide Dual-In-Line package
Y 20-pin Surface Mount (SO) wide-body package
System Block Diagram
Connection Diagram
Surface Mount and Dual-In-Line
Package
C1995 National Semiconductor Corporation TL H 10399
TL H 10399 – 4
Top View
TL H 10399 – 1
Order Number MF10AJ or MF10CCJ
See NS Package Number J20A
Order Number MF10ACWM or
MF10CCWM
See NS Package Number M20B
Order Number MF10ACN or
MF10CCN
See NS Package Number N20A
RRD-B30M115 Printed in U S A

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MF10CCN pdf
Typical Performance Characteristics (Continued)
fCLK fO Deviation
vs Clock Frequency
fCLK fO Deviation
vs Clock Frequency
Deviation of fCLK
vs Nominal Q fO
Deviation of fCLK
vs Nominal Q fO
Pin Descriptions
LP(1 20) BP(2 19) The second order lowpass bandpass
N AP HP(3 18) and notch allpass highpass outputs
These outputs can typically sink 1 5 mA
and source 3 mA Each output typically
swings to within 1V of each supply
INV(4 17)
The inverting input of the summing op-
amp of each filter These are high im-
pedance inputs but the non-inverting in-
put is internally tied to AGND making
INVA and INVB behave like summing
junctions (low impedance current in-
puts)
S1(5 16)
S1 is a signal input pin used in the all-
pass filter configurations (see modes 4
and 5) The pin should be driven with a
source impedance of less than 1 kX If
S1 is not driven with a signal it should be
tied to AGND (mid-supply)
TL H 10399 – 3
SA B(6)
This pin activates a switch that connects
one of the inputs of each filter’s second
summer to either AGND (SA B tied to
Vb) or to the lowpass (LP) output (SA B
tied to Va) This offers the flexibility
needed for configuring the filter in its
various modes of operation
VAa(7) VDa(8)
Analog positive supply and digital posi-
tive supply These pins are internally
connected through the IC substrate and
therefore VAa and VDa should be de-
rived from the same power supply
source They have been brought out
separately so they can be bypassed by
separate capacitors if desired They
can be externally tied together and by-
passed by a single capacitor
VAb(14) VDb(13) Analog and digital negative supplies
The same comments as for VAa and
VDa apply here
5

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MF10CCN arduino
2 0 Modes of Operation (Continued)
MODE 3a HP BP LP and Notch with External Op Amp
(See Figure 11 )
0 0fO
e fCLK c
R2
or
fCLK
c
R2
100 R4 50
R4
0R2 R3
Qe
c
R4 R2
R2
HOHP
e
b
R1
R3
HOBP
e
b
R1
R4
HOLP
e
b
R1
0 0fn
e notch frequency e fCLK Rh or fCLK Rh
100 RI
50 RI
HON e gain of notch at
 Jf e fO e
Q
Rg
RI
HOLP
b
Rg
Rh
HOHP
xHn1 e gain of notch (as f
0)
e
Rg
RI
c
HOLP
 JxHn2 e gain of notch as f
fCLK
2
e
bRg
Rh
c
HOHP
MODE 4 Allpass Bandpass Lowpass Outputs
(See Figure 12 )
fO e center frequency
e fCLK or fCLK
100 50
fz e center frequency of the complex zero fO
Q
e
fO
R3
e
BW R2
R3
QZ
e
quality
factor
of
complex
zero
pair
e
R1
For AP output make R1 e R2
 JHOAP e Allpass gain
at 0 k f k fCLK
2
R2
e b e b1
R1
xHOLP e Lowpass gain (as f
0)
 JR2
eb
a 1 e b2
R1
HOBP e Bandpass gain (at f e fO)
 J  JR3 R2
R3
eb 1a eb2
R2 R1
R2
Circuit Dynamics HOBP e (HOLP) c Q e (HOAP a 1)Q
Due to the sampled data nature of the filter a slight mismatch of fz and fO
occurs causing a 0 4 dB peaking around fO of the allpass filter amplitude
response (which theoretically should be a straight line) If this is unaccept-
able Mode 5 is recommended
FIGURE 11 MODE 3a
TL H 10399 – 20
FIGURE 12 MODE 4
11
TL H 10399 – 21

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