|
|
PDF MAX5864 Data sheet ( Hoja de datos )
| Número de pieza | MAX5864 | |
| Descripción | Ultra-Low-Power / High-Dynamic- Performance / 22Msps Analog Front End | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX5864 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
|
No Preview Available !
19-2915; Rev 1; 10/03
EVAALVUAAILTAIOBNLEKIT
Ultra-Low-Power, High-Dynamic-
Performance, 22Msps Analog Front End
General Description
The MAX5864 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5864 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1VP-P full-scale signals. Typical I-Q channel
phase matching is ±0.1° and amplitude matching is
±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc
spurious-free dynamic range (SFDR) at fIN = 5.5MHz and
fCLK = 22Msps. The DACs’ analog I-Q outputs are fully
differential with ±400mV full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase match is
±0.15° and amplitude match is ±0.05dB. The DACs also
feature dual 10-bit resolution with 71.7dBc SFDR, and
57dB SNR at fOUT = 2.2MHz and fCLK = 22MHz.
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
tion. The typical operating power is 42mW at fCLK =
22Msps with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5864 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5864 operates on a +2.7V to +3.3V ana-
log power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
5.6mA in idle mode and 1µA in shutdown mode. The
MAX5864 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5864ETM
MAX5864E/D
-40°C to +85°C
-40°C to +85°C
48 Thin QFN-EP*
(7mm x 7mm)
Dice**
*EP = Exposed paddle.
**Contact factory for dice specifications.
Pin Configuration appears at end of data sheet.
Features
o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
o Ultra-Low Power
42mW at fCLK = 22MHz (Transceiver Mode)
34mW at fCLK = 15.36MHz (Transceiver Mode)
Low-Current Idle and Shutdown Modes
o Excellent Dynamic Performance
48.5dB SINAD at fIN = 5.5MHz (ADC)
71.7dB SFDR at fOUT = 2.2MHz (DAC)
o Excellent Gain/Phase Match
±0.1° Phase, ±0.03dB Gain at fIN = 5.5MHz (ADC)
o Internal/External Reference Option
o +1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
o Multiplexed Parallel Digital Input/Output for
ADCs/DACs
o Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)
o Evaluation Kit Available (Order MAX5865EVKIT)
Functional Diagram
IA+
IA-
QA+
QA-
ID+
ID-
QD+
QD-
REFP
COM
REFN
REFIN
ADC
ADC
OUTPUT
MUX
ADC
DAC
DAC
INPUT
MUX
DAC
REF AND
BIAS
SERIAL
INTERFACE
AND SYSTEM
CONTROL
MAX5864
DA0–DA7
CLK
DD0–DD9
DIN
SCLK
CS
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
DAC ANALOG OUTPUT
Full-Scale Output Voltage
Output Common-Mode Range
VFS
ADC-DAC INTERCHANNEL CHARACTERISTICS
CONDITIONS
MIN TYP MAX UNITS
1.29
±400
1. 5
mV
V
ADC-DAC Isolation
ADC-DAC TIMING CHARACTERISTICS
ADC fINI = fINQ = 5.5MHz, DAC fOUTI =
fOUTQ = 2.2MHz, fCLK = 22MHz
75 dB
CLK Rise to I-ADC Channel-I
Output Data Valid
tDOI Figure 3 (Note 4)
7.4 9
ns
CLK Fall to Q-ADC Channel-Q
Output Data Valid
tDOQ Figure 3 (Note 4)
6.9 9
ns
I-DAC Data to CLK Fall Setup
Time
tDSI Figure 4 (Note 4)
10 ns
Q-DAC Data to CLK Rise Setup
Time
tDSQ Figure 4 (Note 4)
10 ns
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold Time
Clock Duty Cycle
tDHI
tDHQ
Figure 4 (Note 4)
Figure 4 (Note 4)
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
Figure 5 (Note 4)
DIN to SCLK Setup Time
tDS Figure 5 (Note 4)
DIN to SCLK Hold Time
tDH Figure 5 (Note 4)
SCLK Pulse Width High
tCH Figure 5 (Note 4)
SCLK Pulse Width Low
tCL Figure 5 (Note 4)
SCLK Period
tCP Figure 5 (Note 4)
SCLK to CS Setup Time
tCS Figure 5 (Note 4)
CS High Pulse Width
tCSW Figure 5 (Note 4)
MODE RECOVERY TIMING CHARACTERISTICS
0
0
50
±15
2.6
10
10
0
25
25
50
0
80
ns
ns
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
From shutdown to Tx mode, Figure 6, DAC
settles to within 1 LSB error
20
40
µs
_______________________________________________________________________________________ 5
5 Page 
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
DAC CHANNEL-QD TWO-TONE
SPECTRAL PLOT
0
f1 = 2.0MHz, f2 = 2.2MHz, -7dBFS
-10
-20
DAC ACPR SPECTRAL PLOT
-20
-30
fCLK = 15.36Msps
WCDMA
-40
-30 f1
-40
f2
-50
-60
-50 -70
-60 -80
-70 -90
-80 -100
-90 -110
-100
1
3579
FREQUENCY (MHz)
11
-120
CENTER = 4MHz, SPAN = 7MHz
SUPPLY CURRENT vs. SAMPLING RATE
16
Xcrv MODE
14
12
IVDD
10
8
6
4
IOVDD
2
0
7 10 13 16 19 22
SAMPLING RATE (MHz)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
ADC INTEGRAL NONLINEARITY
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
32 64 96 128 160 192 224 256
DIGITAL OUTPUT CODE
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
DAC INTEGRAL NONLINEARITY
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
DAC DIFFERENTIAL NONLINEARITY
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
REFERENCE OUTPUT VOLTAGE
vs.TEMPERATURE
0.520
0.515
0.510
0.505
0.500
-40
-15 10 35 60
TEMPERATURE (°C)
85
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MAX5864.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX5863 | Ultra-Low-Power / High-Dynamic Performance / 7.5Msps Analog Front End | Maxim Integrated |
| MAX5864 | Ultra-Low-Power / High-Dynamic- Performance / 22Msps Analog Front End | Maxim Integrated |
| MAX5865 | Ultra-Low-Power / High-Dynamic- Performance / 40Msps Analog Front End | Maxim Integrated |
| MAX5866 | 60Msps Analog Front End |  Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |