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PDF MAX5858AECM Data sheet ( Hoja de datos )
| Número de pieza | MAX5858AECM | |
| Descripción | Dual / 10-Bit / 300Msps / DAC with 4x/2x/1x Interpolation Filters and PLL | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2999; Rev 0; 10/03
EVAALVUAAILTAIOBNLEKIT
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
General Description
The MAX5858A dual, 10-bit, 300Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The MAX5858A
integrates two 10-bit DAC cores, 4x/2x/1x programmable
digital interpolation filters, phase-lock loop (PLL) clock
multiplier, and a 1.24V reference. The MAX5858A sup-
ports single-ended and differential modes of operation.
The MAX5858A dynamic performance is maintained over
the entire power-supply operating range of 2.7V to 3.3V.
The analog outputs support a compliance voltage of
-1.0V to +1.25V.
The 4x/2x/1x programmable interpolation filters feature
excellent passband distortion and noise performance.
Interpolating filters minimize the design complexity of
analog reconstruction filters while lowering the data bus
and the clock speeds of the digital interface. The PLL
multiplier generates all internal, synchronized high-
speed clock signals for interpolating filter operation and
DAC core conversion. The internal PLL helps minimize
system complexity and lower cost. To reduce the I/O pin
count, the DAC can also operate in interleave data
mode. This allows the MAX5858A to be updated on a
single 10-bit bus.
The MAX5858A features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-
chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref-
erence can be disabled and an external reference can
be applied for high-accuracy applications.
The MAX5858A features full-scale current outputs of
2mA to 20mA and operates from a 2.7V to 3.3V single
supply. The DAC supports three modes of power-con-
trol operation: normal, low-power standby, and com-
plete power-down. In power-down mode, the operating
current is reduced to 1µA.
The MAX5858A is packaged in a 48-pin TQFP with
exposed paddle (EP) for enhanced thermal dissipation
and is specified for the extended (-40°C to +85°C) opera-
ting temperature range.
Applications
Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Direct Digital Synthesis
Instrumentation/ATE
Features
o 10-Bit Resolution, Dual DAC
o 300Msps Update Rate
o Integrated 4x/2x/1x Interpolating Filters
o Internal PLL Multiplier
o 2.7V to 3.3V Single Supply
o Full Output Swing and Dynamic Performance at
2.7V Supply
o Superior Dynamic Performance
73dBc SFDR at fOUT = 20MHz
UMTS ACLR = 63dB at fOUT = 30.7MHz
o Programmable Channel Gain Matching
o Integrated 1.24V Low-Noise Bandgap Reference
o Single-Resistor Gain Control
o Interleave Data Mode
o Differential Clock Input Modes
o EV Kit Available—MAX5858AEVKit
Ordering Information
PART
TEMP RANGE
MAX5858AECM
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
48 TQFP-EP*
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
DA9/PD 1
DA8/DACEN 2
DA7/F2EN 3
DA6/F1EN 4
DA5/G3 5
DGND 6
DVDD 7
DA4/G2 8
DA3/G1 9
DA2/G0 10
DA1 11
DA0 12
EP
MAX5858A
36 REFO
35 REN
34 PLLF
33 PGND
32 PVDD
31 CLKXN
30 CLKXP
29 PLLEN
28 LOCK
27 CW
26 DB0
25 DB1
13 14 15 16 17 18 19 20 21 22 23 24
TQFP-EP
NOTE: EXPOSED PADDLE CONNECTED TO GND.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference,
VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C
guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
Output Settling Time
Output Rise Time
Output Fall Time
Data-to-CLK Rise Setup Time
(Note 3)
Data-to-CLK Rise Hold Time
(Note 3)
Data-to-CLK Fall Setup Time
(Note 3)
Data-to-CLK Fall Hold Time
(Note 3)
Control Word to CW Fall Setup
Time
Control Word to CW Fall Hold
Time
CW High Time
CW Low Time
DACEN Rise-to-VOUT Stable
PD Fall-to-VOUT Stable
Clock Frequency at
CLKXP/CLKXN Input
SYMBOL
ts
tDCSR
tDCHR
tDCSF
tDCHF
CONDITIONS
To ±0.1% error band (Note 2)
10% to 90% (Note 2)
90% to 10% (Note 2)
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
tCWS
tCWH
tSTB
tPDSTB
External reference
fCLKDIFF Differential clock, PLL disabled
MIN TYP MAX UNITS
11 ns
2.5 ns
2.5 ns
1.5
ns
2.2
0.4
ns
1.4
1.8
ns
2.4
1.2
ns
1.3
2.5 ns
2.5 ns
5
5
0.7
0.5
ns
ns
µs
ms
300 MHz
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
tCXD PLL disabled
4.6 ns
Minimum CLKXP/CLKXN Clock
High Time
tCXH
1.5 ns
Minimum CLKXP/CLKXN Clock
Low Time
tCXL
1.5 ns
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
AVDD
IAVDD
DVDD
(Note 4)
2.7 3.3 V
45 49 mA
2.7 3.3 V
_______________________________________________________________________________________ 5
5 Page 
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
Typical Operating Characteristics (continued)
(AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA,
differential output, TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
0.30
0.20
0.10
0
-0.10
-0.20
-0.30
0
RL = 0
150 300 450 600 750 900 1050
DIGITAL INPUT CODE
POWER DISSIPATION
vs. fDAC
450
fOUT = 5MHz
400
350
NO INTERPOLATION
300
250
200
0
34 68 102 136 165
fDAC (MHz)
1050
950
850
750
650
550
450
350
0
POWER DISSIPATION
vs. fDAC
2x INTERPOLATION
4x INTERPOLATION
50 100 150 200 250 300
fDAC (MHz)
1000
900
800
700
600
500
400
300
200
2.7
POWER DISSIPATION
vs. SUPPLY VOLTAGE
2x INTERPOLATION
fCLK = 200MHz
fOUT = 5MHz
4x INTERPOLATION
fCLK = 200MHz
fOUT = 5MHz
NO INTERPOLATION
fCLK = 165MHz
fOUT = 5MHz
2.8 2.9 3.0 3.1 3.2
SUPPLY VOLTAGE (V)
3.3
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
2.7 2.8 2.9 3.0 3.1 3.2 3.3
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
-40
-15 10 35 60
TEMPERATURE (°C)
85
______________________________________________________________________________________ 11
11 Page | ||
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| PDF Descargar | [ Datasheet MAX5858AECM.PDF ] | |
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