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PDF M48T559Y Data sheet ( Hoja de datos )
| Número de pieza | M48T559Y | |
| Descripción | 64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M48T559Y
64 Kbit (8Kb x8) TIMEKEEPER® SRAM
with ADDRESS/DATA MULTIPLEXED
s SOFTWARE and HARDWARE RESET for
WATCHDOG TIMER
s REGISTER COMPATIBLE with M48T59
TIMEKEEPER SRAM
s ADDRESS/DATA MULTIPLEXED I/O PINS
s WATCHDOG TIMER - MONITORS OUT of
CONTROL PROCESSOR or HUNG BUS
s ALARM with WAKE-UP in BATTERY MODE
s INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
s FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGE
(VPFD = Power-fail Deselect Voltage):
– M48T559Y: 4.2V ≤ VPFD ≤ 4.5V
s PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP
CONTAINS the BATTERY and CRYSTAL
s MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
s PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE
DESCRIPTION
The M48T559Y TIMEKEEPER® RAM is an 8K x 8
non-volatile static RAM and real time clock. The
monolithic chip is available in the SNAPHAT pack-
age to provide a highly integrated battery backed-
up memory and real time clock solution.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
February 2000
SNAPHAT (SH)
Battery/Crystal
28
1
SOH28 (MH)
Figure 1. Logic Diagram
AS0
AS1
W
R
RSTIN1
RSTIN2
E
WDI
VCC
8
AD0-AD7
M48T559Y
RST
IRQ/FT
VSS
AI01674B
1/18
1 page  
M48T559Y
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70 °C)
Symbol
Parameter
Min
Typ
Max
Unit
VPFD Power-fail Deselect Voltage
4.2 4.35 4.5 V
VSO Battery Back-up Switchover Voltage
3.0 V
tDR (2) Expected Data Retention Time
Note: 1. All voltages referenced to VSS.
2. At 25°C.
7
YEARS
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C)
Symbol
Parameter
Min Max Unit
tPD E at VIH before Power Down
0 µs
tF (1)
VPFD (max) to VPFD (min) VCC Fall Time
300 µs
tFB (2)
VPFD (min) to VSS VCC Fall Time
10 µs
tR VPFD (min) to VPFD (max) VCC Rise Time
10 µs
tRB VSS to VPFD (min) VCC Rise Time
1 µs
tREC
VPFD (max) to RST High
40 200 ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
es VPFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
RST
tPD
INPUTS
RECOGNIZED
tFB
OUTPUTS
VALID
(PER CONTROL INPUT)
tDR tR
tRB
tREC
DON'T CARE
HIGH-Z
RECOGNIZED
VALID
(PER CONTROL INPUT)
AI01384D
5/18
5 Page 
M48T559Y
For more information on calibration, see the Appli-
cation Note AN934 "TIMEKEEPER Calibration".
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time.
SETTING ALARM CLOCK
Registers 1FF5h-1FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific day of the month or
repeat every day, hour, minute, or second. It can
also be programmed to go off while the M48T559Y
is in the battery back-up mode of operation to
serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 11 shows the possible configura-
tions. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date registers and RPT1-4.
The alarm flag and the IRQ/FT output are cleared
by a read to the Flags register as shown in Figure
11.
Note: If an alarm condition occurs while the flags
register address is latched into the address buffer,
the alarm flag will not be set until an address other
than the flags register (1FF0h) is latched into the
address buffer. This will insure that the alarm flag
will not be inadvertently reset while reading the
flag register. To properly check to see if an alarm
condition has occurred while reading the flag reg-
ister, the user is required to latch, read or write to
an alternate address and then re-read the alarm
flag.
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T559Y was in the deselect mode
during power-up. Figure 12 illustrates the back-up
mode alarm timing.
Table 11. Alarm Repeat Mode
RPT4 RPT3 RPT2 RPT1 Alarm Activated
1 1 1 1 Once per Second
1 1 1 0 Once per Minute
1 1 0 0 Once per Hour
1 0 0 0 Once per Day
0 0 0 0 Once per Month
Figure 10. Interrupt Reset Waveforms
AD0-AD7
R
ACTIVE FLAG BIT
IRQ/FT
ADDRESS 1FF0h
AI01677B
11/18
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