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PDF PI90LV387 Data sheet ( Hoja de datos )
| Número de pieza | PI90LV387 | |
| Descripción | High-Speed Differential Line Drivers | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI90LV387/ PI90LVB387
High-Speed Differential Line Drivers
Features
• Sixteen line drivers meet or exceed the requirements of the
ANSI EIA/TIA-644 Standard
• Designed for signaling rates up to 500 Mbps with very low
radiation (EMI)
• Low voltage differential signaling with typical output voltage
of 350mV into :
– 100Ω load (PI90LV387)
– 50Ω load (PI90LVB387)
• Propagation delay times less than 2.6ns
• Output skew is less than 150ps
• Part-to-part skew is less than 1.5ns
• 35mW total power dissipation in each driver operating at 200
MHz
• Bus-pin ESD protection exceeds 10kV
• Low voltage TTL (LVTTL) logic inputs are 5V tolerant
• Packaging (Pb-free & Green available):
-64-Pin TSSOP (A)
Pin Diagram
GND 1
64 1DO1+
VCC 2
63 1DO1 –
VCC 3
62 1DO2+
GND 4
61 1DO2 –
EN1 5
60 1DO3+
1DIN1 6
59 1DO3 –
1DIN2 7
58 1DO4+
1DIN3 8
57 1DO4 –
1DIN4 9
56 2DO1+
EN2 10
55 2DO1 –
2DIN1 11
54 2DO2+
2DIN2 12
53 2DO2–
2DIN3 13 64-Pin 52 2DO3+
2DIN4 14
A 51 2DO3 –
GND 15
50 2DO4+
VCC 16
49 2DO4 –
VCC 17
48 3DO1+
GND 18
47 3DO1 –
3DIN1 19
46 3DO2+
3DIN2 20
45 3DO2 –
3DIN3 21
44 3DO3+
3DIN4 22
43 3DO3 –
EN3 23
42 3DO4+
4DIN1 24
41 3DO4 –
4DIN2 25
40 4DO1+
4DIN3 26
39 4DO1 –
4DIN4 27
37 4DO2+
EN3 28
37 4DO2 –
GND 29
36 4DO3+
VCC 30
35 4DO3 –
VCC 31
34 4DO4+
GND 32
33 4DO4 –
Description
PI90LV387/ PI90LVB387 consists of sixteen differential line
drivers that implement the electrical characteristics of low-volt-
age differential signaling (LVDS). This signaling technique lowers
output voltage levels to reduce power, increase switching speeds,
and allow operation with a 3V supply rail.
The intended application of this device and signaling technique
is for point-to-point baseband (single termination) and multi-
point (double termination) data transmission over a controlled
impedance media of approximately 100Ω and 50Ω (LVB387).
The transmission media may be printed-circuit board traces, back-
planes, or cables. The large number of drivers integrated into the
same substrate, with the low pulse skew of balanced signaling,
allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion
16-channel receivers, the PI90LV386 or PI90LVT386, over 400
million data transfers per second in single-edge clocked systems
are possible with very little power.
(Note: The ultimate rate and distance of data transfer is dependent
upon attenuation characteristics of the media, the noise coupling
to the environment, and other system characteristics.)
The drivers are enabled in groups of five. When disabled, driver
outputs are at a high impedance. Each driver input (DIN) and en-
able (EN) have an internal pulldown that drives the input to a low
level when open circuited.
The parts are characterized for operation from –40°C to 85°C.
Block Diagram
DIN1
DO1+
DO1–
DIN2
EN
DIN3
DO2+
DO2–
DO3+
DO3–
DIN4
1 of 4
DO4+
DO4–
1
PS8573C
09/22/04
1 page  
Parameter Measurement Information
PI90LV387/PI90LVB387
High-Speed Differential Line Drivers
Figure 1. Voltage and Current Definitions
Figure 2. VOD Test Circuit
Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤1ns, Pulse Repetition Rate
(PRR) = 50 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T. The measurement
of VOC(PP) is made on test equipment with a –3dB bandwidth of at least 300MHz.
5
PS8573C
09/22/04
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI90LV387.PDF ] | |
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