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PDF PI7C8140A Data sheet ( Hoja de datos )
| Número de pieza | PI7C8140A | |
| Descripción | 2 PORT PCI TO PCI BRIDGE | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI7C8140A
2-Port PCI-to-PCI Bridge
REVISION 1.01
07-0067
3545 North First Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Internet: http://www.pericom.com
1 page  
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
TABLE OF CONTENTS
1 SIGNAL DEFINITIONS.............................................................................................................................11
1.1 SIGNAL TYPES....................................................................................................................................11
1.2 SIGNALS ..............................................................................................................................................11
1.2.1 PRIMARY BUS INTERFACE SIGNALS ...................................................................................11
1.2.2 SECONDARY BUS INTERFACE SIGNALS .............................................................................12
1.2.3 CLOCK SIGNALS ........................................................................................................................14
1.2.4 MISCELLANEOUS SIGNALS ....................................................................................................14
1.2.5 POWER AND GROUND..............................................................................................................14
1.3 PIN LIST – 128-PIN QFP......................................................................................................................15
2 PCI BUS OPERATION...............................................................................................................................16
2.1 TYPES OF TRANSACTIONS..............................................................................................................16
2.2 SINGLE ADDRESS PHASE ................................................................................................................17
2.3 DEVICE SELECT (DEVSEL#) GENERATION..................................................................................17
2.4 DATA PHASE.......................................................................................................................................17
2.5 WRITE TRANSACTIONS ...................................................................................................................17
2.5.1 MEMORY WRITE TRANSACTIONS.........................................................................................18
2.5.2 MEMORY WRITE AND INVALIDATE .....................................................................................18
2.5.3 DELAYED WRITE TRANSACTIONS ........................................................................................19
2.5.4 WRITE TRANSACTION BOUNDARIES...................................................................................20
2.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS..............................................................20
2.5.6 FAST BACK-TO-BACK TRANSACTIONS ................................................................................20
2.6 READ TRANSACTIONS .....................................................................................................................20
2.6.1 PREFETCHABLE READ TRANSACTIONS .............................................................................21
2.6.2 DYNAMIC PREFETCHING CONTROL....................................................................................21
2.6.3 NON-PREFETCHABLE READ TRANSACTIONS ...................................................................21
2.6.4 READ PREFETCH ADDRESS BOUNDARIES ........................................................................22
2.6.5 DELAYED READ REQUESTS ...................................................................................................22
2.6.6 DELAYED READ COMPLETION WITH TARGET .................................................................23
2.6.7 DELAYED READ COMPLETION ON INITIATOR BUS.........................................................23
2.6.8 FAST BACK-TO-BACK READ TRANSACTIONS ....................................................................24
2.7 CONFIGURATION TRANSACTIONS ...............................................................................................24
2.7.1 TYPE 0 ACCESS TO PI7C8140A................................................................................................25
2.7.2 TYPE 1 TO TYPE 0 CONVERSION ...........................................................................................25
2.7.3 TYPE 1 TO TYPE 1 FORWARDING ..........................................................................................26
2.7.4 SPECIAL CYCLES.......................................................................................................................27
2.8 TRANSACTION TERMINATION.......................................................................................................27
2.8.1 MASTER TERMINATION INITIATED BY PI7C8140A ..........................................................28
2.8.2 MASTER ABORT RECEIVED BY PI7C8140A .........................................................................29
2.8.3 TARGET TERMINATION RECEIVED BY PI7C8140A ...........................................................29
2.8.4 TARGET TERMINATION INITIATED BY PI7C8140A...........................................................31
3 ADDRESS DECODING..............................................................................................................................33
3.1 ADDRESS RANGES ............................................................................................................................33
3.2 I/O ADDRESS DECODING .................................................................................................................33
3.2.1 I/O BASE AND LIMIT ADDRESS REGISTER .........................................................................34
3.2.2 ISA MODE ....................................................................................................................................34
3.3 MEMORY ADDRESS DECODING.....................................................................................................35
3.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ..................................35
3.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ..........................36
07-0067
Page 5 of 82
March 20, 2007 – Revision 1.01
5 Page 
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
1 SIGNAL DEFINITIONS
1.1 SIGNAL TYPES
SIGNAL TYPE
I
O
P
TS
STS
OD
DESCRIPTION
Input only
Output only
Power
Tri-state bi-directional
Sustained tri-state. Active LOW signal must be pulled HIGH for 1 cycle
when deasserting.
Open Drain
1.2 SIGNALS
Signals that end with “#” are active LOW.
1.2.1 PRIMARY BUS INTERFACE SIGNALS
Name
P_AD[31:0]
P_CBE#[3:0]
P_PAR
P_FRAME#
P_IRDY#
Pin Number
121, 122, 123, 124,
125, 126, 127, 2, 5, 6,
7, 8, 9, 10, 12, 13, 25,
26, 27, 28, 30, 31, 32,
33, 35, 36, 37, 40, 41,
42, 43, 44
3, 14, 24, 34
23
15
16
Type
TS
TS
TS
STS
STS
Description
Primary Address / Data: Multiplexed address and data bus.
Address is indicated by P_FRAME# assertion. Write data is
stable and valid when P_IRDY# is asserted and read data is
stable and valid when P_TRDY# is asserted. Data is transferred
on rising clock edges when both P_IRDY# and P_TRDY# are
asserted. During bus idle, PI7C8140A drives P_AD to a valid
logic level when P_GNT# is asserted.
Primary Command/Byte Enables: Multiplexed command field
and byte enable field. During address phase, the initiator drives
the transaction type on these pins. After that, the initiator drives
the byte enables during data phases. During bus idle, PI7C8140A
drives P_CBE#[3:0] to a valid logic level when P_GNT# is
asserted.
Primary Parity. Parity is even across P_AD[31:0],
P_CBE#[3:0], and P_PAR (i.e. an even number of 1’s). P_PAR
is an input and is valid and stable one cycle after the address
phase (indicated by assertion of P_FRAME#) for address parity.
For write data phases, P_PAR is an input and is valid one clock
after P_IRDY# is asserted. For read data phase, P_PAR is an
output and is valid one clock after P_TRDY# is asserted. Signal
P_PAR is tri-stated one cycle after the P_AD lines are tri-stated.
During bus idle, PI7C8140A drives P_PAR to a valid logic level
when P_GNT# is asserted.
Primary FRAME (Active LOW). Driven by the initiator of a
transaction to indicate the beginning and duration of an access.
The de-assertion of P_FRAME# indicates the final data phase
requested by the initiator. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
Primary IRDY (Active LOW). Driven by the initiator of a
transaction to indicate its ability to complete current data phase
on the primary side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
07-0067
Page 11 of 82
March 20, 2007 – Revision 1.01
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PI7C8140A.PDF ] | |
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