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PDF PI74AVC+16821K Data sheet ( Hoja de datos )
| Número de pieza | PI74AVC+16821K | |
| Descripción | 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
Product Features
PI74AVC+16821 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
IOFF supports partial power-down operation
3.6V I/O Tolerant Inputs and Outputs
All outputs contain a patented DDC
(Dynamic Drive Control) circuit that reduces noise
without degrading propagation delay
Industrial operation: 40°C to +85°C
Available Packages:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (K)
Description
Pericom Semiconductors PI74AVC+ series of logic circuits are
produced using the Companys advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+ 16821is a 20-bit bus interface flip-flop designed for
1.65V to 3.6V VCC operation. It can be used as two 10-bit flip-flops
or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current sinking
capability of the driver.
Logic Block Diagram
1
1OE
1CLK 56
1D1 55
One of Ten
Channels
C1
1D
2OE 28
2CLK 29
2
1Q1
2D1 42
One of Ten
Channels
C1
1D
15
2Q1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
1 PS8548 07/31/01
1 page  
PI74AVC+16821
2.5V 20-Bit Bus Interface
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345F67l8i9p0-1F23l4o5p678w90i1t2h3435-6S78t9a0t1e21O234u5t6p78u90t1s2
Timing requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
fclock Clock frequency
tw Pulse duration, CLK high or low
tsu Setup time, data before CLK
th Hold time, data after CLK
VCC = 1.2V
Min. Max.
4.1
1.7
VCC = 1.5V VCC = 1.8V
± 0.1V
± 0.15V
Min. Max. Min. Max.
160
3.1
2.7 2.1
1.3 1.0
VCC = 2.5V
± 0.2V
Min. Max.
200
2.5
1.5
1.0
VCC = 3.3V
± 0.3V
Min. Max.
200
2.5
1.4
1.0
Units
ns
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Parameters
fmax
tpd
ten
tdis
From
(Input)
CLK
OE
OE
To
(Output)
Q
Q
Q
VCC = 1.2V
Typ.
6.8
6.8
5.4
VCC = 1.5V VCC = 1.8V
± 0.1V
± 0.15V
Min. Max. Min. Max.
160
1.5 4.5 1.2 4.0
1.6 4.5 1.6 4.0
2.5 4.2 2.3 3.6
VCC = 2.5V
± 0.2V
Min. Max.
200
0.8 3.2
0.9 3.3
1 3.4
VCC = 3.3V
± 0.3V
Min. Max.
200
0.7 2.8
0.7 3.0
1.5 3.4
Units
ns
Operating Characteristics, TA= 25°C
Parameters
Cpd Power Dissipation Capacitance
Outputs Enabled
Outputs Disabled
Test Conditions
CL = 0pF,
f = 10 MHz
VCC = 1.8V
±0.15V
Typical
90
66
VCC = 2.5V
±0.2V
Typical
100
72
VCC = 3.3V
±0.3V
Typical
110
78
Units
pF
5 PS8548 07/31/01
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI74AVC+16821K.PDF ] | |
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