PDF PI49FCT3804S Data sheet ( Hoja de datos )

Número de pieza	PI49FCT3804S
Descripción	3.3V Fast CMOS Buffer/Clock Driver
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! PI49FCT3804 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 3.3V Fast CMOS Buffer/Clock Driver Features • 3.3V version of PI49FCT804T • Low output skew: 0.7ns • Clock busing with Hi-Z state control • TTL input and output levels, reducing problematic “ground bounce” • Extremely low static power (1mW, typical) • Hysteresis on all inputs • ESD protection exceeds 2000V • Industrial Operation: –40°C to 85°C • Packaging (Pb-free & Green available): – 16-pin 300-mil wide plastic SOIC (S) Description Pericom Semiconductor’s PI49FCT3804 is a non-inverting clock driver designed with two independent groups of buffers. These buffers have Hi-Z state Output Enable inputs (active LOW) with a 1-in, 4-out configuration per group. Each clock driver consists of two banks of drivers, driving four outputs each from a standard TTL compatible CMOS input. Block Diagram OEA INA INB OEB Pin Configuration 4 OA3-OA0 4 OB3-OB0 OA0 OA1 OA2 GND OA3 GND OEA INA 1 16 2 15 3 16-Pin 14 4 S 13 5 12 6 11 7 10 89 VCC OB0 OB1 OB2 GND OB3 OEB INB 1 PS7043F 09/24/04 1 page PI49FCT3804 3.3V Buffer/Clock Driver1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 Switching Characteristics over Operating Range 3804 Parameters Description Com. Conditions(1) Min. Max. 3804A Com. Min. Max. Units tPLH tPHL Propagation Delay INA to OAN, INB to OBN CL = 50pF 1.5 6.5 1.5 5.8 ns RL = 500Ω tPZH tPZL Output Enable Time OEA to OAN, OEB to OBN 1.5 8.0 1.5 8.0 ns tPHZ tPLZ tskew(o)(3) Output Disable Time OEA to OAN, OEB to OBN Skew between two outputs of same package 1.5 7.0 1.5 7.0 ns — 0.8 — 0.7 ns (same transition) tskew(p)(3) Skew between opposite transitions (tPHL-tPLH) of the same output — 1.0 — 0.8 ns tskew(t)(3) Skew between two outputs of different package at — 1.6 — 1.4 ns same temperature (same transition) Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worse cast temperature (max. temp). Tests Circuits For All Outputs(1) VCC 6.0V Pulse Generator VIN VOUT D.U.T. RT 500Ω 50pF CL 500Ω Switch Position Test Disable LOW Enable LOW Disable HIGH Enable HIGH All Other Inputs Switch 6V GND Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 5 PS7043F 09/24/04 5 Page

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