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PDF PHP125N06LT Data sheet ( Hoja de datos )
| Número de pieza | PHP125N06LT | |
| Descripción | TrenchMOS transistor Logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP125N06LT, PHB125N06LT
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 55 V
ID = 75 A
RDS(ON) ≤ 8 mΩ (VGS = 5 V)
RDS(ON) ≤ 7 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP125N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB125N06LT is supplied in the SOT404 surface mounting package.
PINNING
PIN DESCRIPTION
1 gate
SOT78 (TO220AB)
tab
SOT404
tab
2 drain 1
3 source
tab drain
1 23
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 13
75
75
240
250
175
UNIT
V
V
V
A
A
A
W
˚C
March 1998
1
Rev 1.400
1 page  
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP125N06LT, PHB125N06LT
2.5 a
BUK959-60 Rds(on) normlised to 25degC
2
1.5
1
0.5
-100
-50
0 50 100 150 200
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0 50
Tj / C
100 150 200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ 98%
1E-04
1E-05
1E-05
0 0.5 1 1.5 2 2.5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
3
12
10
8
6
Ciss
4
2
0
0.01 0.1
1 VDS/V
10
Coss
Crss
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
6
VGS/V
5
4
VDS = 14V
VDS = 44V
3
2
1
0
0 10 20 30 40 50 60 70 80 90
QG/nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
100
IF/A
80
60
Tj/C = 175
25
40
20
0
0 0.2 0.4 0.6 0.8 1 1.2
VSDS/V
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
March 1998
5
Rev 1.400
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PHP125N06LT.PDF ] | |
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