|
|
PDF M58LW064D Data sheet ( Hoja de datos )
| Número de pieza | M58LW064D | |
| Descripción | 64 Mbit (8Mb x8 / 4Mb x16 / Uniform Block) 3V Supply Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M58LW064D (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
M58LW064D
64 Mbit (8Mb x8, 4Mb x16, Uniform Block)
3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
s WIDE x8 or x16 DATA BUS for HIGH
BANDWIDTH
s SUPPLY VOLTAGE
– VDD = VDDQ = 2.7 to 3.6V for Program, Erase
and Read operations
s ACCESS TIME
– Random Read 110ns
– Page Mode Read 110/25ns
s PROGRAMMING TIME
– 16 Word Write Buffer
– 12µs Word effective programming time
s 64 UNIFORM 64 KWord/128KByte MEMORY
BLOCKS
s BLOCK PROTECTION/ UNPROTECTION
s PROGRAM and ERASE SUSPEND
s 128 bit PROTECTION REGISTER
s COMMON FLASH INTERFACE
s 100, 000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code M58LW064D: 0017h
Figure 1. Packages
TSOP56 (N)
14 x 20 mm
TBGA
TBGA64 (ZA)
10 x 13 mm
December 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/51
1 page  
M58LW064D
SUMMARY DESCRIPTION
The M58LW064D is a 64 Mbit (8Mb x 8 or 4Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7V to 3.6V)
core supply.
The memory is divided into 64 blocks of 1Mbit that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input VPEN is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the enabled memory and to set
the device in power-down mode.
The STS signal is an open drain output that can be
used to identify the Program/Erase Controller sta-
tus. It can be configured in two modes: Ready/
Busy mode where a static signal indicates the sta-
tus of the P/E.C, and Status mode where a pulsing
signal indicates the end of a Program or Block
Erase operation. In Status mode it can be used as
a system interrupt signal, useful for saving CPU
time.
The Bus operations of the device are controlled by
Output Enable, Write Enable and three different
Chip Enables. Refer to Table 2, Device Enable, for
all possible combinations to enable and disable
the device. Together they allow simple, yet power-
ful, connection to most microprocessor, often with-
out additional logic.
The device includes a 128 bit Protection Register.
The Protection Register is divided into two 64 bit
segments, the first one is written by the manufac-
turer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10x13mm, 1mm pitch) packages.
5/51
5 Page 
M58LW064D
sistor. The use of an open-drain output allows the
STS pins from several memories to be connected
to a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active
Program/Erase Enable (VPEN). The Program/
Erase Enable input, VPEN, is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
It is recommended to power-up and power-down
VDD and VDDQ together to avoid any condition that
would result in data corruption.
VSS Ground. Ground, VSS, is the reference for
the core power supply. It must be connected to the
system ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS.
Note: Each device in a system should have
VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 8, AC Measurement Load Circuit.
Table 2. Device Enable
E2
E1
VIL VIL
VIL VIL
VIL VIH
VIL VIH
VIH VIL
VIH VIL
VIH VIH
VIH VIH
Note: For single device operations, E2 and E1 can be connected to VSS.
E0
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Device
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
11/51
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M58LW064D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M58LW064 | 64 Mbit x16 and x16/x32 / Block Erase Low Voltage Flash Memories | ST Microelectronics |
| M58LW064C | 64 Mbit (4Mb x16 / Uniform Block / Burst) 3V Supply Flash Memory | ST Microelectronics |
| M58LW064D | 64 Mbit (8Mb x8 / 4Mb x16 / Uniform Block) 3V Supply Flash Memory | ST Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |