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Número de pieza | M54HCT273 | |
Descripción | OCTAL D TYPE FLIP FLOP WITH CLEAR | |
Fabricantes | ST Microelectronics | |
Logotipo | ||
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No Preview Available ! M54HCT273
M74HCT273
OCTAL D TYPE FLIP FLOP WITH CLEAR
. HIGH SPEED
fMAX = 80 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. PIN AND FUNCTION COMPATIBLE WITH
54/74LS273
B1R
(Plastic Package)
M 1R
(Micro Package)
F1R
(Ceramic Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT273 is a high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated in sili-
con gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption. Information signals
applied to D inputs are transferred to the Q outputs
on the positive-going edge of the clock pulse.
When the CLEAR input is held low, the Q output are
in the low logic level independent of the other inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age. This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are de-
signed to directly interface HSC2MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption. All inputs are equipped with
protection circuits against static discharge and tran-
sient excess voltage.
ORDER CODES :
M54HCT273F1R M74HCT273M1R
M74HCT273B1R M74HCT273C1R
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
February 1993
NC =
No Internal
Connection
1/10
1 page M54/M74HCT273
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 4.5
tTHL Time
9 15 19 22 ns
tPLH Propagation
tPHL Delay Time
(CLOCK - Q)
4.5
19 30 38 45 ns
tPLH Propagation
tPHL Delay Time
(CLEAR - Q)
4.5
22 32 40 48 ns
fMAX Maximum Clock 4.5
Frequency
30 71
24
MHz
CIN
CPD (*)
Input Capacitance
Power Dissipation
Capacitance
5 10 10 10 pF
29 pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/8 (per Flip FLop), and the
total CPD when n pcs of Flip Flop operate can be gained by the following equations: CPD (total) = 32 + 11 x n
SWITCHING CHARACTERISTICS TEST WAVEFORM
TEST CIRCUIT ICC (Opr.)
5/10
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet M54HCT273.PDF ] |
Número de pieza | Descripción | Fabricantes |
M54HCT27 | TRIPLE 3-INPUT NOR GATE | ST Microelectronics |
M54HCT273 | OCTAL D TYPE FLIP FLOP WITH CLEAR | ST Microelectronics |
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