PDF MC14046B Data sheet ( Hoja de datos )

Número de pieza	MC14046B
Descripción	Phase Locked Loop
Fabricantes	ON Semiconductor
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No Preview Available ! MC14046B Phase Locked Loop The MC14046B phase locked loop contains two phase comparators, a voltage−controlled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs, PCAin and PCBin. Input PCAin can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The self−bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1out, and maintains 90° phase shift at the center frequency between PCAin and PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2out and LD, and maintains a 0° phase shift between PCAin and PCBin signals (duty cycle is immaterial). The linear VCO produces an output signal VCOout whose frequency is determined by the voltage of input VCOin and the capacitor and resistors connected to pins C1A, C1B, R1, and R2. The source−follower output SFout with an external resistor is used where the VCOin signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage−to−frequency conversion and motor speed control. Features • Buffered Outputs Compatible with Low−Power TTL • Diode Protection on All Inputs • Supply Voltage Range = 3.0 to 18 V • Pin−for−Pin Replacement for CD4046B • Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited • Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle Limited • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter http://onsemi.com SOIC−16 WB DW SUFFIX CASE 751G SOEIAJ−16 F SUFFIX CASE 966 MARKING DIAGRAMS 16 16 14046BG AWLYYWW MC14046B ALYWG 11 SOIC−16 WB SOEIAJ−16 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid ap- plications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper op- eration, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused out- puts must be left open. Value Unit VDD DC Supply Voltage Range −0.5 to +18.0 V Vin Input Voltage Range (All Inputs) −0.5 to VDD + 0.5 V Iin DC Input Current, per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Operating Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 14 1 Publication Order Number: MC14046B/D 1 page MC14046B PCAin 14 @ FREQUENCY f′ 3 PCBin PHASE COMPARATOR 2 OR 13 PC1out OR PC2out VCOin 9 SOURCE 10 FOLLOWER SFout RSF EXTERNAL LOW-PASS FILTER EXTERNAL ÷N COUNTER 9 VCO 11 12 R1 R2 6 CIA CI 4 7 CIB VCOout @ FREQUENCY Nf′ = f Typical Low−Pass Filters (a) R3 (a) R3 INPUT ǸOUTPUT INPUT C2 2fC [ 1 p 2 p fL R3 C2 OUTPUT R4 C2 Typically: R4 C2 + 6N fmax – N 2pDf (R3 ) 3, 000W) C2 + 100NDf fmax2 – R4 C2 D f = fmax − fmin NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint to ground. The value for CC should be such that the corner frequency of this network does not significantly affect Wn. In Figure B, the ratio of R3 to R4 sets the damping, R4 ^ (0.1)(R3) for optimum results. LOW−PASS FILTER Definitions: N = Total division ratio in feedback loop Kφ = VDD/π for Phase Comparator 1 Kφ = VDD/4 π for Phase Comparator 2 2 p D fVCO KVCO + VDD – 2 for a typical design V Wn ^ 2 p fr 10 (at phase detector input) ζ ^ 0.707 Filter A Ǹwn + KfKVCO NR3C2 Filter B Ǹwn + KfKVCO NC2(R3 ) R4) z + Nwn 2KfKVCO F(s) + 1 R3C2S ) 1 z + 0.5 wn (R3C2 ) KfKNVCO) F(s) + R3C2S ) 1 S(R3C2 ) R4C2) ) 1 PCAin PCBin PC1out VCOin Phase Comparator 1 VDD VSS VOH VOL VOH VOL VOH VOL Waveforms PCAin PCBin LD PC2out VCOin Phase Comparator 2 Note: for further information, see: (1) F. Gardner, “Phase−Lock Techniques”, John Wiley and Son, New York, 1966. (2) G. S. Moschytz, “Miniature RC Filters Using Phase−Locked Loop”, BSTJ, May, 1965. (3) Garth Nash, “Phase−Lock Loop Design Fundamentals”, AN−535, Motorola Inc. (4) A. B. Przedpelski, “Phase−Locked Loop Design Articles”, AR254, reprinted by Motorola Inc. Figure 3. General Phase−Locked Loop Connections and Waveforms VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL http://onsemi.com 5 5 Page

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