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PDF MC13001XP Data sheet ( Hoja de datos )
| Número de pieza | MC13001XP | |
| Descripción | MONOMAX BLACK AND WHITE TV SUBSYSTEM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Monomax Black and White
TV Subsystem
The MONOMAX is a single chip IC that will perform the electronic
functions of a monochrome TV receiver, with the exception of the tuner,
sound channel, and power output stages. The MC13001XP and
MC13007XP will function as a drop–in replacement for the MC13001P and
MC13007P, but some external IF components can be removed for maximum
benefit. IF AGC range has been increased, video output impedance lowered,
and horizontal driver output current capability increased.
• Full Performance Monochrome Receiver with Noise and Video
Processing (Black Level Clamp, DC Contrast, Beam Limiter)
• Video IF Detection On–Chip (No Coils, No Pins, except Inputs)
• Noise Filtering On–Chip (Minimum Pins and Externals)
• Oscillator Components On–Chip (No Precision Capacitors Required)
• MC13001XP for 525 Line NTSC and MC13007XP for 625 Line CCIR
• Low Dissipation in All Circuit Sections
• High Performance Vertical Countdown
• 2–Loop Horizontal System with Low Power Startup Mode
• Noise Protected Sync and Gated AGC System
• Designed to work with TDA1190P or TDA3190P Sound IF and Audio
Output Devices
Order this document by MC13001X/D
MC13001X
MC13007X
MONOMAX
BLACK AND WHITE TV
SUBSYSTEM
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 710
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC13001XP
MC13007XP TA = 0° to +70°C
Plastic DIP
IF In 3
IF In 5
RF AGC 11
RF AGC Delay 10
AGC 9
Flyback 15
Horizontal Sync
Separator
7
VCC 18
+8.0V Out 19
VIF IF Decoupling
42 6
Figure 1. Basic Elements of the System
Sound
IF
28
Black
Clamp
Contrast
Beam Limit
26 25 27
Video IF
VIF
Detector
Video
Process
Video Process
Blank
Buffer
AGC Sync
RF
AGC
AGC
Feed Forward
Flyback
Buffer
AGC
Sync
Separator
Noise
Process
Regulator
Horizontal
Phase
Detector 2
Vertical
Integrator
Vertical
Vertical
Sync
Separator
Window
Control
& Reset
BClock
525
Vertical
Preamp
Vertical
Ramp
Phase
Detector 1
B2
31.5 kHz
Oscillator
Variable
Slicer
B2 Horizontal
Buffer
24 Video Out
8 AGC Filter
23 Vertical Sync
22 Vertical Out
21
Vertical
Feedback
20 Vertical Size
17 Horizontal Out
13
Horizontal Phase
Detector 1
MOTOROLA ANALOG IC DEVICE DATA
12
Horizontal Frequency
14
Horizontal Phase
Detector 2
© Motorola, Inc. 1995
1
1 page  
MC13001X MC13007X
The composite sync is stripped from a delayed and filtered
video in a peak detecting type of sync separator. The
components connected to Pin 7 determine the slice and tilt
levels of the sync separator. For ideal horizontal sync
separation and to ensure correct operating of AGC anti–
lockup circuit, a relatively short time constant is required at
Pin 7. This time constant is less than optimum for good noise
free vertical separation, giving rise to a vertical slice level
near sync tip. An additional longer time–constant is therefore
coupled to the first via a diode. With the correct choice of time
constants, the diode is non–conducting during the horizontal
sync period, but conducts during the longer vertical period.
This connects the longer time constant to the sync separator
for the vertical period and stops the slice level from moving up
the sync tip. The separated composite sync is integrated
internally, and the time constant is such that only the longer
period vertical pulses produce a significant output pulse. The
output is then fed to the vertical sync separator, which further
processes the vertical pulse and provides increased noise
protection. The selection of the external components
connected to the vertical separator at Pin 23 permits a wide
range of performance options. A simple resistor divider from
the 8.2 V regulated supply gives adequate performance for
most conditions. The addition of an RC network will make the
slice level adapt to varying sync amplitude and give improved
weak signal performance. A resistor to the AGC voltage on
Pin 9 enables the sync slice level to be changed as a function
of signal level. This further improves the low signal level
separation while at the same time giving increased impulse
noise protection on strong signals.
Horizontal Oscillator
The horizontal PLL (see Figure 7) is a two–loop system
using a 31.5 kHz oscillator which after a divider stage is
locked to the sync pulse using Phase Detector 1. The control
signal derived from this phase detector on Pin 13 is fed via a
high–value resistor to the frequency–control point on Pin 12.
The same divided oscillator frequency is also fed to Phase
Detector 2, where the flyback pulse is compared with it and
the resulting error used to change a variable slice level on the
oscillator ramp waveform. This therefore changes the timing
of the output square wave from the slicer and hence the
timing of the buffered horizontal output on Pin 17 (see
Figure 8). The error on Phase Detector 2 is reduced until the
phasing of the flyback pulse is correct with respect to the
divided oscillator waveform, and hence with respect to the
sync pulse.
Figure 8. Horizontal Waveforms
200 mVpp
4.5 V 7
50 mVpp
6.0 V 13
2.0 V 17
0V
+0.9 V 15
0V
–0.7 V
To improve the pull–in and noise characteristics of the first
PLL, the phase detector current is increased when the
vertical lock indicator signals an unlocked condition and is
decreased when locked. This increases the loop bandwidth
and pull–in range when out of lock, and decreases the loop
bandwidth when in lock, thus improving the noise
performance. In addition, the phase detector current during
the vertical period is reduced in order to minimize the
disturbance to the horizontal caused by the longer period
vertical phase detector pulses.
31.5kHz
Oscillator
Vary
Frequency
Figure 7. Horizontal Oscillator Systems
SLICE
Divide
by 2
Output
17
SLICE
Divide
by 2
Phase
Detector 2
Vary
SLICE
Level
(Phase)
14
12 13
Phase
Detector 1
Sync
15
Flyback
Deflection
MOTOROLA ANALOG IC DEVICE DATA
5
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