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PDF MC12439FN Data sheet ( Hoja de datos )
| Número de pieza | MC12439FN | |
| Descripción | HIGH FREQUENCY PLL CLOCK GENERATOR | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
High Frequency Clock Generator
MC12439
The MC12439 is a general purpose synthesized clock source targeting
applications that require both serial and parallel interfaces. Its internal
VCO will operate over a range of frequencies from 400 to 800MHz. The
differential PECL output can be configured to be the VCO frequency
divided by 1, 2, 4, or 8. With the output configured to divide the VCO
frequency by 1, and with a 16.66MHz external quartz crystal used to
provide the reference frequency, the output frequency can be specified in
16.66MHz steps.
HIGH FREQUENCY PLL
CLOCK GENERATOR
• 50 to 800MHz Differential PECL Outputs
• ±25ps Typical Peak–to–Peak Output Jitter
• Minimal Frequency Over–Shoot
• Synthesized Architecture
• Serial 3–Wire Interface
• Parallel Interface for Power–Up
• Quartz Crystal Interface
• 28–Lead PLCC Package
• Operates from 3.3V or 5.0V Power Supply
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776–02
Functional Description
The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference
oscillator is sent directly to the phase detector. With a 16.66MHz crystal, this provides a reference frequency of 16.66MHz.
Although this data sheet illustrates functionality only for a 16MHz and 16.66MHz crystal, any crystal in the 10–20MHz range can
be used. In addition to the crystal, an LVCMOS input can also be used as the PLL reference. The reference is selected via the
XTAL_SEL input pin.
The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This
divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
in 50Ω to VCC – 2.0.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the
PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
1/97
© Motorola, Inc. 1997
1
REV 3
1 page  
MC12439
SCLOCK
FREF
MCNT
PLL 12439
M COUNTER
VCO_CLK
0
1
SEL_CLK
Shift Reg Out
SDATA SHIFT
REG
12–BIT
T0
T1
T2
LATCH
SLOAD
Reset
PLOADB
DECODE
N DIVIDE
(1, 2, 4, 8)
FOUT
(VIA ENABLE GATE)
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
7
TEST
MUX
0
TEST
• T2=T1=1, T0=0: Test Mode
• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Figure 4. Serial Test Clock Block Diagram
DC CHARACTERISTICS (TA = 0 to 70°C; VCC = 3.3 to 5.0V ±5%)
Symbol
Characteristic
Min Typ
Max
VIH Input HIGH Voltage
2.0
VIL Input LOW Voltage
IIN Input Current
IOH Output HIGH Current (Note 1.)
(FOUT/FOUT Only)
0.8
1.0
50
VOH
VOL
VOH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
TEST
TEST
FOUT
FOUT
2.5
2.27
0.4
2.47
VOL
Output LOW Voltage
FOUT
FOUT
1.49
1.68
ICC
Power Supply Current
VCC
PLL_VCC
90 110
15 20
1. Maximum IOH spec implies the device can drive 25Ω impedance with the PECL outputs.
2. See Applications Information section for output level versus frequency information.
3. Output levels will vary 1:1 with VCC variation.
4. 50Ω to VCC – 2.0V pulldown.
Unit Condition
V VCC = 3.3 to 5.0V
V VCC = 3.3 to 5.0V
mA
mA Continuous Current
V IOH = –0.8mA, (Note 2.)
V IOL = 0.8mA, (Note 2.)
V VCC = 3.3V (Notes 3., 4.)
V VCC = 3.3V (Notes 3., 4.)
mA
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
5 Page 
MC12439
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
INTERNET: http://www.mot.com/sps/
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
TIMING SOLUTIONS
BR1333 — Rev 6
◊
*MC12439/D*MC12439/D
11 MOTOROLA
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