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PDF MC12430FA Data sheet ( Hoja de datos )
| Número de pieza | MC12430FA | |
| Descripción | HIGH FREQUENCY PLL CLOCK GENERATOR | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
High Frequency Clock Generator
The MC12430 is a general purpose synthesized clock source targeting
applications that require both serial and parallel interfaces. Its internal
VCO will operate over a range of frequencies from 400 to 800MHz. The
differential PECL output can be configured to be the VCO frequency
divided by 1, 2, 4 or 8. With the output configured to divide the VCO
frequency by 2, and with a 16.000MHz external quartz crystal used to
provide the reference frequency, the output frequency can be specified in
1MHz steps. The PLL loop filter is fully integrated so that no external
components are required.
• 50 to 800MHz Differential PECL Outputs
• ±25ps Peak–to–Peak Output Jitter
• Fully Integrated Phase–Locked Loop
• Minimal Frequency Over–Shoot
• Synthesized Architecture
• Serial 3–Wire Interface
• Parallel Interface for Power–Up
• Quartz Crystal Interface
• 28–Lead PLCC Package
• Operates from 3.3V or 5.0V Power Supply
MC12430
HIGH FREQUENCY PLL
CLOCK GENERATOR
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776–02
Functional Description
The internal oscillator uses the external quartz crystal as the basis of
its frequency reference. The output of the reference oscillator is divided
by 8 before being sent to the phase detector. With a 16MHz crystal, this
provides a reference frequency of 2MHz. Although this data sheet
illustrates functionality only for a 16MHz crystal, any crystal in the
10–20MHz range can be used.
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4 or 8).
This divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
in 50Ω to VCC – 2.0. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase–locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
2/97
© Motorola, Inc. 1997
1
REV 1
1 page  
MC12430
SCLOCK
FREF
MCNT
PLL 12430
M COUNTER
VCO_CLK
0
1
SEL_CLK
SDATA SHIFT
REG
14–BIT
T0
T1
T2
LATCH
SLOAD
Reset
PLOADB
DECODE
N DIVIDE
(1, 2, 4, 8)
FOUT
(VIA ENABLE GATE)
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
7
TEST
MUX
0
TEST
• T2=T1=1, T0=0: Test Mode
• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Figure 2. Serial Test Clock Block Diagram
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%)
Symbol
Characteristic
Min Typ
VIH Input HIGH Voltage
2.0
VIL Input LOW Voltage
IIN Input Current
VOH
Output HIGH Voltage
2.17
VOL
Output LOW Voltage
1.41
ICC
Power Supply Current
VCC
PLL_VCC
85
15
1. Output levels will vary 1:1 with VCC0 variation.
Max Unit
Condition
V VCC = 3.3 to 5.0V
0.8 V VCC = 3.3 to 5.0V
1.0 mA
2.50 V VCC0 = 3.3V1
1.76 V VCC0 = 3.3V1
100 mA
20
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
5 Page 
MC12430
OUTLINE DIMENSIONS
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
A1
32
A
4X
0.20 (0.008) AB T–U Z
25
1
–T–
B
B1
8
DETAIL Y
–U–
V
17 V1
9
–Z– 4X
9 S1
0.20 (0.008) AC T–U Z
S
–AB–
SEATING
PLANE
–AC–
G
0.10 (0.004) AC
8X M_
CE
R
DETAIL AD
BASE
METAL
FÉÉÉNÉÉÉ D
J
SECTION AE–AE
W
H
K
X
Q_
DETAIL AD
AE
P
DETAIL Y
AE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 7.000 BSC
0.276 BSC
A1 3.500 BSC
0.138 BSC
B 7.000 BSC
0.276 BSC
B1 3.500 BSC
0.138 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC
0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
M 12_ REF
12_ REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC
0.016 BSC
Q 1_ 5_ 1_ 5 _
R 0.150 0.250 0.006 0.010
S 9.000 BSC
0.354 BSC
S1 4.500 BSC
0.177 BSC
V 9.000 BSC
0.354 BSC
V1 4.500 BSC
0.177 BSC
W 0.200 REF
0.008 REF
X 1.000 REF
0.039 REF
TIMING SOLUTIONS
BR1333 — Rev 6
11
MOTOROLA
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MC12430FA.PDF ] | |
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