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PDF MC10E175 Data sheet ( Hoja de datos )
| Número de pieza | MC10E175 | |
| Descripción | 9-BIT LATCH WITH PARITY | |
| Fabricantes | ON Semiconductor | |
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MC10E175, MC100E175
5V ECL 9-Bit Latch With
Parity
Description
The MC10E/100E175 is a 9-bit latch. It also features a tenth latched
output, ODDPAR, which is formed as the odd parity of the nine data
inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by using D8 as the
parity-type select (L = even parity, H = odd parity), and using
ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a logical high and
makes the latch transparent when placed at a logic low level.
Features
• 9-Bit Latch
• Parity Detection/Generation
• 800 ps Max. D to Output
• Reset
• PECL Mode Operating Range: VCC = 4.2 V to 5.5 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.5 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Charged Device MOdel; > 2 kV
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 416 devices
• Pb−Free Packages are Available*
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE175FNG
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 9
1
Publication Order Number:
MC10E175/D
1 page  
MC10E175, MC100E175
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
0°C 25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
fMAX
tPLH
tPHL
Maximum Toggle Frequency
Propagation Delay to Output
700 1100
700 1100
700
D to Q 550 800 975 550 800 975 550
D to ODDPAR 950 1400 1600 950 1400 1600 950
LEN to Q 525 800 975 525 800 975 525
LEN to ODDPAR 525 800 975 525 800 975 525
MR to Q(tPHL) 525 800 975 525 800 975 525
MR to ODDPAR(tPHL) 525 800 975 525 800 975 525
ts Setup Time
D (Q) 275 100
275
275
D (ODDPAR) 900 700
900
900
th Hold Time
D (Q) 175 −100
175
175
D (ODDPAR) − 300 − 70
− 300
− 300
tRR
tSKEW
Reset Recovery Time
Within-Device Skew (Note 10)
LEN, MR
850
600
75
850 600
75
850
D to Q
75
75
D to ODDPAR
200
200
tJITTER
tr
tf
Random Clock Jitter (RMS)
Rise/Fall Times
(20 - 80%)
<1 <1
300 500 800 300 500 800 300
85°C
Typ
1100
800
1400
800
800
800
800
600
75
75
200
<1
500
Max
975
1600
975
975
975
975
Unit
MHz
ps
ps
ps
ps
ps
ps
ps
800
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / −0.06 V.
100 Series: VEE can vary −0.46 V / −0.8 V.
10. Within-device skew is defined as identical transitions on similar paths through a device.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC10E175.PDF ] | |
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