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PDF MC10E1652 Data sheet ( Hoja de datos )
| Número de pieza | MC10E1652 | |
| Descripción | Dual ECL Output Comparator | |
| Fabricantes | ON Semiconductor | |
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MC10E1652
5V, -5V Dual ECL Output
Comparator with Latch
The MC10E1652 is fabricated using ON Semiconductor’s advanced
MOSAIC III process and is output compatible with 10H logic devices.
In addition, the device is available in a 20-pin surface mount package.
However, the MC10E1652 provides user programmable hysteresis.
The latch enable (LENa and LENb) input pins operate from standard
ECL 10H logic levels. When the latch enable is at a logic high level,
the MC10E1652 acts as a comparator; hence, Q will be at a logic high
level if V1 > V2 (V1 is more positive than V2). Q is the complement
of Q. When the latch enable input goes to a low logic level, the outputs
are latched in their present state, providing the latch enable setup and
hold time constraints are met. The level of input hysteresis is
controlled by applying a bias voltage to the HYS pin.
Features
• Typical 3.0 dB Bandwidth > 1.0 GHz
• Typical V to Q Propagation Delay of 775 ps
• Typical Output Rise/Fall of 350 ps
• Common Mode Range −2.0 V to +3.0 V
• Individual Latch Enables
• Differential Outputs
• Operating Mode: VCC = 5.0 V, VEE = −5.2 V, GND = 0 V
• Programmable Input Hysteresis
• No Internal Input Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 3
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−O @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 85 devices
• These are Pb−Free Devices*
http://onsemi.com
MARKING
DIAGRAM
1 20
20 1
PLCC−20
FN SUFFIX
CASE 775
MC10E
1652FNG
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
April, 2013 − Rev. 10
1
Publication Order Number:
MC10E1652/D
1 page  
MC10E1652
APPLICATIONS INFORMATION
The timing diagram (Figure 5.) is presented to illustrate
the MC10E1652’s compare and latch features. When the
signal on the LEN pin is at a logic high level, the device is
operating in the “compare mode,” and the signal on the input
arrives at the output after a nominal propagation delay (tPHL,
tPLH). The input signal must be asserted for a time, ts, prior
to the negative going transition on LEN and held for a time,
th, after the LEN transition. After time th, the latch is
operating in the “latch mode,” thus transitions on the input
do not appear at the output. The device continues to operate
in the “latch mode” until the latch is asserted once again.
Moreover, the LEN pulse must meet the minimum pulse
width (tpw) requirement to effect the correct input-output
relationship. Note that the LEN waveform in Figure 5.
shows the LEN signal swinging around a reference labeled
VBBINT; this waveform emphasizes the requirement that
LEN follow typical ECL 10KH logic levels because
VBBINT is the internally generated reference level, hence is
nominally at the ECL VBB level.
Finally, VOD is the input voltage overdrive and represents
the voltage level beyond the threshold level (VTHR) to which
the input is driven. As an example, if the threshold level is
set on one of the comparator inputs as 80 mV and the input
signal swing on the complementary input is from zero to 100
mV, the positive going overdrive would be 20 mV and the
negative going overdrive would be 80 mV. The result of
differing overdrive levels is that the devices have shorter
propagation delays with greater overdrive because the
threshold level is crossed sooner than the case of lower
overdrive levels. Typically, semiconductor manufactures
refer to the threshold voltage as the input offset voltage
(VOS) since the threshold voltage is the sum of the
externally supplied reference voltage and inherent device
offset voltage.
VBBINT
LEN
V
VTHR
VIN
Q
Q
ts th
VOD
tPHL
tpw
tPLH(LEN)
Figure 5. Input/Output Timing Diagram
http://onsemi.com
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC10E1652.PDF ] | |
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