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PDF MC100EL51 Data sheet ( Hoja de datos )
| Número de pieza | MC100EL51 | |
| Descripción | Differential Clock D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
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MC10EL51, MC100EL51
5 V ECL Differential Clock
D Flip‐Flop
Description
The MC10EL/100EL51 is a differential clock D flip-flop with reset.
The device is functionally similar to the E151 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E151 the EL51 is ideally
suited for those applications which require the ultimate in AC
performance.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EL51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input (pulled down to VEE) conditions.
The 100 Series contains temperature compensation.
Features
• 475 ps Propagation Delay
• 2.8 GHz Toggle Frequency
• ESD Protection:
♦ > 1 kV Human Body Model
♦ > 100 V Machine Model
• PECL Mode Operating Range:
♦ VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range:
♦ VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on D, R, and CLK
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity:
♦ Level 1 for SOIC−8 NB
♦ Level 3 for TSSOP−8
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating:
♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 73 devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8 NB
D SUFFIX
CASE 751−07
8
1
TSSOP−8
DT SUFFIX
CASE 948R−02
MARKING DIAGRAMS*
8
HEL51
ALYW
G
1
8
HL51
ALYWG
G
1
8
KEL51
ALYW
G
1
8
KL51
ALYWG
G
1
H = MC10
K = MC100
4X = MC10
2M = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping†
MC10EL51DG
SOIC−8
(Pb-Free)
98 Units/Tube
MC10EL51DR2G
SOIC−8 2500/Tape & Reel
(Pb-Free)
MC10EL51DTG
TSSOP−8
(Pb-Free)
100 Units/Tube
MC100EL51DG
SOIC−8
(Pb-Free)
98 Units/Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 8
1
Publication Order Number:
MC10EL51/D
1 page  
MC10EL51, MC100EL51
Table 8. AC CHARACTERISTICS (VCC= 5.0 V; VEE= 0.0 V or VCC= 0.0 V; VEE= −5.0 V (Note 1))
Symbol
fmax
tPLH
tPHL
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
CLK
R
−40°C
Min Typ Max
1.8 2.8
25°C
Min Typ Max
2.2 2.8
Min
2.2
325 465 605 385 475 565 440
305 455 605 355 465 565 410
tS Setup Time
tH Hold Time
tRR Reset Recovery
tPW Minimum Pulse Width
CLK, Reset
150 0
250 100
400 200
400
150 0
250 100
400 200
400
150
250
400
400
VPP
tJITTER
tr
tf
Input Swing (Note 2)
Cycle-to-Cycle Jitter
Output Rise/Fall Times Q
(20% − 80%)
150 1000 150 1000 150
TBD
TBD
100 225 350 100 225 350 100
1. 10 Series: VEE can vary +0.25 V / −0.5 V.
100 Series: VEE can vary +0.8 V / −0.5 V.
2. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
85°C
Typ
2.8
Max
530 620
510 620
0
100
200
TBD
225
1000
350
Unit
GHz
ps
ps
ps
ps
ps
mV
ps
ps
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC100EL51.PDF ] | |
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