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PDF LMX2512 Data sheet ( Hoja de datos )
| Número de pieza | LMX2512 | |
| Descripción | PLLatinum Frequency Synthesizer System with Integrated VCO | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 2003
LMX2502/LMX2512
PLLatinum™ Frequency Synthesizer System with
Integrated VCO
General Description
LMX2502 and LMX2512 are highly integrated, high perfor-
mance, low power frequency synthesizer systems optimized
for Korean PCS and Korean Cellular CDMA (1xRTT, IS-95)
mobile handsets. Using a proprietary digital phase locked
loop technique, LMX2502 and LMX2512 generate very
stable, low noise local oscillator signals for up and down
conversion in wireless communications devices.
LMX2502 and LMX2512 include a voltage controlled oscil-
lator (VCO), a loop filter, and a fractional-N RF PLL based on
a delta sigma modulator. In concert these blocks form a
closed loop RF synthesizer system. LMX2502 supports the
Korean PCS band and LMX2512 supports the Korean Cel-
lular band.
LMX2502 and LMX2512 include an Integer-N IF PLL also.
For more flexible loop filter designs, the IF PLL includes a
4-level programmable charge pump. Together with an exter-
nal VCO and loop filter, LMX2502 and LMX2512 make a
complete closed loop IF synthesizer system.
Serial data is transferred to the device via a three-wire
MICROWIRE interface (DATA, LE, CLK).
Operating supply voltage ranges from 2.7 V to 3.3 V.
LMX2502 and LMX2512 feature low current consumption:
17 mA at 2.8 V.
LMX2502 and LMX2512 are available in a 28-pin leadless
leadframe package (LLP).
Features
n Small Size
5.0 mm X 5.0 mm X 0.75 mm 28-Pin LLP Package
n RF Synthesizer System
Integrated RF VCO
Integrated Loop Filter
Low Spurious, Low Phase Noise Fractional-N RF PLL
Based on 11-Bit Delta Sigma Modulator
10 kHz Frequency Resolution
n IF Synthesizer System
Integer-N IF PLL
Programmable Charge Pump Current Levels
Programmable Frequency
n Supports Various Reference Frequencies
19.20/19.68 MHz
n Fast Lock Time: 500 µs
n Low Current Consumption
17 mA at 2.8 V
n 2.7 V to 3.3 V Operation
n Digital Filtered Lock Detect Output
n Hardware and Software Power Down Control
Applications
n Korean PCS CDMA Systems
n Korean Cellular CDMA Systems
Functional Block Diagram
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200680
20068001
www.national.com
1 page  
Electrical Characteristics (VCC = VDD = 2.8 V, TA = 25 ˚C; unless otherwise noted) (Continued)
Symbol
IF PLL
fFin
Parameter
Operating Frequency LMX2502LQ1635
(Note 8)
LMX2512LQ0967
LMX2512LQ1065
PFin
fΦIF
ICPout
IF Input Sensitivity
Phase Detector Frequency
Charge Pump Current
DIGITAL INTERFACE (DATA, CLK, LE, LD, CE)
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
IIH High-Level Input Current
IIL Low-Level Input Current
Input Capacitance
VOH High-Level Output Voltage
VOL Low-Level Output Voltage
Output Capacitance
MICROWIRE INTERFACE TIMING
tCS
tCH
tCWH
tCWL
tES
tEW
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
Clock to Latch Enable Set Up Time
Latch Enable Pulse Width
Condition
Min
Typ
Max
Units
IF_FREQ [1:0] = 10,
440.76
Default Value
IF_FREQ [1:0] = 00,
170.76
Default Value
IF_FREQ [1:0] = 01,
367.20
Default Value
-10
120
IF_CUR [1:0] = 00
100
IF_CUR [1:0] = 01
200
IF_CUR [1:0] = 10
300
IF_CUR [1:0] = 11
800
0
MHz
MHz
MHz
dBm
kHz
µA
µA
µA
µA
0.8 VDD
0.8 VCC
0
0
-10
VDD
VCC
0.2 VDD
0.2 VCC
10
V
V
V
V
µA
-10 10 µA
3 pF
0.9 VDD
0.9 VCC
0.1 VDD
0.1 VCC
5
V
V
V
V
pF
50 -
10 -
50 -
50 -
50 -
50 -
- ns
- ns
- ns
- ns
- ns
- ns
Note 4: In power down mode, set DATA, CLK, and LE pins to 0 V (GND).
Note 5: The reference frequency must also be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact National
Semiconductor.
Note 6: For other frequency ranges, please contact National Semiconductor.
Note 7: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/- 1 kHz
of the final frequency.
Note 8: Frequencies other that the default value can be programmed using Words R4 and R5. See Programming Description for details.
5 www.national.com
5 Page 
Programming Description (Continued)
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The SPI_DEF bit selects between using the default IF counter values and user programmable values. The use of the default
counter values requires that only words R0 to R3 (registers R3, loaded first, to R0, loaded last) be sent after initial power up.
The RF_LD bit activates the lock detect output of the LD pin (pin 19). The lock detect mode shows the lock status of the RF PLL.
The waveform of the lock detect mode is shown in Figure 1, in the Functional Description section on LOCK DETECT.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
11-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0 REGISTER
MSB
SHIFT REGISTER BIT LOCATION
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data Field
Address
Field
R0 SPI_ RF_ RF_ 0 RF_B
(Default) DEF SEL LD
[3:0]
RF_A
[2:0]
RF_FN
[10:0]
00
Name
SPI_DEF
RF_SEL
RF_LD
RF_B [3:0]
RF_A [2:0]
RF_FN [10:0]
Functions
Default Register Selection
0 = OFF (Use values set in R0 to R6)
1 = ON (Use default values set in R0 to R3)
RF VCO Selection
0 = LMX2512
1 = LMX2502
RF Lock Detect
0 = Hard zero (GND)
1 = Lock detect
RF_B Counter
4-bit programmable counter
2 ≤ RF_B ≤ 15
RF_A Counter
3-bit swallow counter
0 ≤ RF_A ≤ 7 for LMX2502
0 ≤ RF_A ≤ 5 for LMX2512
RF Fractional Numerator Counter
11-bit programmable counter
0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz
0 ≤ RF_FN < 1968 for fOSC = 19.68 MHz
11 www.national.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LMX2512.PDF ] | |
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