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PDF LMX2370 Data sheet ( Hoja de datos )
| Número de pieza | LMX2370 | |
| Descripción | PLLatinum Dual Frequency Synthesizer for RF Personal Communications | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
March 1999
LMX2370/LMX2371/LMX2372
PLLatinum™ Dual Frequency Synthesizer for RF
Personal Communications
LMX2370 2.5 GHz/1.2 GHz
LMX2371 2.0 GHz/1.2 GHz
LMX2372 1.2 GHz/1.2 GHz
General Description
The LMX237X family of monolithic, integrated dual fre-
quency synthesizers, including prescalers, is designed to be
used as a first and second local oscillator for dual mode or
dual conversion transceivers. It is fabricated using National’s
0.5u ABiCV silicon BiCMOS process. The LMX237X con-
tains two dual modulus prescalers. A 32/33 or a 16/17
prescaler can be selected for the 2.5 GHz and 2.0 GHz RF
synthesizers with the 16/17 prescaler rated for input frequen-
cies below 1.2 GHz. A 16/17 or an 8/9 prescaler can be se-
lected for the 1.2 GHz RF synthesizers with the 8/9 prescaler
rated for input frequencies below 550 MHz. Using a digital
phase locked loop technique, the LMX237X can generate
very stable, low noise control signals for UHF and VHF volt-
age controlled oscillators (VCO’s). Serial data is transferred
into the LMX237X via a 1.8V three wire interface (Data, En-
able, Clock) compatible with low voltage baseband proces-
sors. Supply voltage can range from 2.7V to 5.5V. The
LMX237X family features very low current consumption typi-
cally: LMX2370 - 6.0 mA @ 3V, LMX2371 - 5.0 mA @ 3V,
LMX2372 - 4.0 mA @ 3V.
The LMX237X are available in a 24-pad chip scale (CSP) or
a 20-pin TSSOP surface mount plastic package.
Features
n 2.7V–5.5V operation
n Ultra low current consumption
n Low phase detector noise floor
n Low voltage MICROWIRE™ interface (1.8V up to VCC)
n Low prescaler values
32/33 @ fIN ≤ 2.5 GHz
16/17 @ fIN ≤ 1.2 GHz
8/9 @ fIN ≤ 550 MHz
n Selectable charge pump current levels
n Selectable FastLock™ mode
n Enhanced ESD protection
n Small 24 pad chip scale package (3.5 x 4.5 x 1.0 mm)
Applications
n Portable wireless communications (PCS/PCN, cordless)
n Dual mode cellular telephone systems
n Spread spectrum communication systems (CDMA)
n Cable TV tuners (CATV)
Functional Block Diagram
FastLock™, PLLatinum™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101026
DS101026-1
www.national.com
1 page  
Electrical Characteristics (VCC = Vp = Vµc = 3.0V; −40˚C < TA < 85˚C except as specified). (Continued)
CHARGE PUMP
Symbol
Parameter
ICPo-source
ICPo-sink
ICPo-source
ICPo-sink
ICPo-TRI
Main and Auxiliary Charge
Pump Output Current (Note 4)
Charge Pump TRI-STATE®
Current
ICPo-sink vs
ICPo-source
ICPo vs
VCPo
ICPo vs TA
CP Sink vs Source Mismatch
CP Current vs Voltage
CP Current vs Temperature
DIGITAL INTERFACE (DATA, CLOCK, LE)
Symbol
Parameter
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
IIH High-Level Input Current
IIL Low-Level Input Current
VOL Low-Level Output Current
Conditions
VCPo = Vp/2, ICPo_4X = 0
VCPo = Vp/2, ICPo_4X = 0
VCPo = Vp/2, ICPo_4X = 1
VCPo = Vp/2, ICPo_4X = 1
0.5 ≤ VCPo ≤ Vp − 0.5,
−40˚C < TA < 85˚C
VCPo = Vp/2, TA = 25˚C
0.5 ≤ VCPo ≤ Vp − 0.5, TA = 25˚C
VCPo = Vp/2, −40˚C < TA < 85˚C
Conditions
Vµc = 1.72V to 5.5V
Vµc = 1.72V to 5.5V
VIH = Vµc = 5.5V
VIL = 0, Vµc = 5.5V
IOL = 1.0 mA, VEXT = 1.8V (Note
5)
Min
−2.5
Min
0.8 Vµc
−1.0
−1.0
Value
Typ
1.0
−1.0
4.0
−4.0
0.1
3
8
8
Value
Typ
0.1
MICROWIRE TIMING
Symbol
Parameter
Conditions
Min
tCS
tCH
tCWH
tCWL
tES
Data to Clock Setup Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Setup
Time
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
20
50
50
50
tEW
Load Enable Pulse Width
See Data Input Timing
50
Note 4: Main and Auxiliary Charge Pump magnitude are controlled by Main_ICPo_4X and Aux_ICPo_4X bits respectively.
Note 5: Lock Detect open drain output only pulled up to VEXT. Typically VEXT = VCC.
Value
Typ
Unit
Max
mA
mA
mA
mA
2.5 nA
10 %
15 %
%
Max
0.2 Vµc
1.0
1.0
0.4
Unit
V
V
µA
µA
V
Unit
Max
ns
ns
ns
ns
ns
ns
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer
such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter. The fre-
quency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feed-
back [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to
obtain a comparison reference frequency. This reference signal (fR) is then presented to the input of a phase/frequency detector
and compared with the feedback signal (fN), which is obtained by dividing the VCO frequency down by way of the N-counter. The
phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control
voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback
signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency
will be N times that of the comparison frequency, where N is the integer divide ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSCin pin.
OSCin can operate up to 50 MHz with input sensitivity of 0.5 VPP. The OSCin pin drives both the Main R-counter and the Auxiliary
R-counter. The input has a VCC/2 input threshold that can be driven from an external CMOS or TTL logic gate. Typically, the OSCin
is connected to the output of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R-COUNTERS)
The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz.
Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767.
5 www.national.com
5 Page 
2.0 Programming Description (Continued)
2.3.5 PLL Prescaler Select (P_Aux, P_Main)
The LMX2370, LMX2371 and LMX2372 contain two dual modulus prescalers. A 32/33 or a 16/17 prescaler can be selected for
the 2.5 GHz and 2.0 GHz RF synthesizers in the LMX2370 and LMX2371 respectively. The 16/17 prescaler is only rated for input
frequencies below 1.2 GHz. A 16/17 or an 8/9 prescaler can be selected for the both 1.2 GHz synthesizers on the LMX2372 as
well as the 1.2 GHz synthesizers on the LMX2370 and LMX2371. The 8/9 prescaler is only rated for input frequencies below
550 MHz.
P_Main, (Main_N18) or
P_Aux (Aux_N18)
0
1
PLL Input Frequency
fIN > 1.2 GHz
550 < fIN < 1200 MHz
fIN < 550 MHz
2.5 GHz PLL
16/17
32/33
2.5 GHz PLL
32/33
16/17 or 32/33
16/17 or 32/33
Prescaler Value
2.0 GHz PLL
16/17
32/33
Allowable Prescaler Values
2.0 GHz PLL
32/33
16/17 or 32/33
16/17 or 32/33
1.2 GHz PLL
8/9
16/17
1.2 GHz PLL
NA
16/17
8/9 or 16/17
2.3.5.1 Pulse Swallow Function
fVCO = [(P x B) + A] x fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B: Preset divide ratio of binary 13-bit programmable counter (3 to 8191)
A: Preset divide ratio of binary 5-bit swallow counter
0 ≤ A ≤ 31 {P=32}
0 ≤ A ≤ 15 {P=16}
0 ≤ A ≤ 7 {P=8}
A≤B
fOSC: Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual modulus prescaler (P = 8, 16, or 32)
2.3.6 PLL Power Down Control (Aux_PWDN, Main_PWDN)
The Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) bits are used to power down either the Main or Auxiliary PLL’s charge
pump portion, or the entire PLL block depending on the setting of the respective charge pump TRI-STATE bit (Aux_CPo_TRI or
Main_CPo_TRI) in the R_CNTR register. The power-down mechanism is described below. The R and N counters for each respec-
tive PLL are disabled and held at reset during the synchronous and asynchronous power down modes. This will allow a smooth
acquisition of the Main RF signal when the oscillator input buffer is still active (Auxiliary loop powered up) and vice versa. Upon
powering up, both R and N counters will start at the “zero” state, and the relationship between R and N will not be random.
Synchronous Power Down Mode
One of the PLL loops can be synchronously powered down by first setting the respective loop’s TRI-STATE mode bit LOW (R17
= 0) and then asserting its power down mode bit (N19 = 1). The power down function is gated by the charge pump. Once the
power down program bits Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) and TRI-STATE bits Aux_CPo_TRI (Aux_R17)
or Main_CPo_TRI (Main_R17) are loaded, the part will go into power down mode upon the completion of a charge pump pulse
event.
Asynchronous Power Down Mode
One of the PLL loops can be asynchronously powered down by first setting the respective loop’s TRI-STATE mode bit HI (R17
= 1) and then asserting its power down mode bit (N19 = 1). The power down function is NOT gated by the charge pump. Once
the power down program bits Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) and its respective TRI-STATE bit Aux_CPo-
_TRI (Aux_R17) or Main_CPo_TRI (Main_R17) are loaded, the part will go into power down mode immediately.
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LMX2370.PDF ] | |
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