|
|
PDF LMS485IM Data sheet ( Hoja de datos )
| Número de pieza | LMS485IM | |
| Descripción | 5V Low Power RS-485 / RS-422 Differential Bus | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LMS485IM (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
April 2003
LMS485
5V Low Power RS-485 / RS-422 Differential Bus
Transceiver
General Description
The LMS485 is a low power differential bus/line transceiver
designed for high speed bidirectional data communication on
multipoint bus transmission lines. It is designed for balanced
transmission lines. It meets ANSI Standards TIA/EIA
RS422-B, TIA/EIA RS485-A and ITU recommendation and
V.11 and X.27. The LMS485 combines a TRI-STATE™ dif-
ferential line driver and differential input receiver, both of
which operate from a single 5.0V power supply. The driver
and receiver have an active high and active low, respec-
tively, that can be externally connected to function as a
direction control. The driver and receiver differential inputs
are internally connected to form differential input/output (I/O)
bus ports that are designed to offer minimum loading to bus
whenever the driver is disabled or when VCC = 0V. These
ports feature wide positive and negative common mode
voltage ranges, making the device suitable for multipoint
applications in noisy environments. The LMS485 is available
in a 8-Pin SOIC and 8-Pin DIP packages. It is a drop-in
socket replacement to Maxim’s MAX485
Features
n Meet ANSI standard RS-485-A and RS-422-B
n Data rate 2.5 Mbps
n Single supply voltage operation, 5V
n Thermal shutdown protection
n Short circuit protection
n Low power BiCMOS
n Allows up to 32 transceivers on the bus
n Open circuit fail-safe for receiver
n Extended operating temperature range −40˚C to 85˚C
n Drop-in replacement to MAX485
n Available in 8-pin SOIC and 8-Pin DIP package
Applications
n Low power RS-485 systems
n Network hubs, bridges, and routers
n Point of sales equipment (ATM, barcode scanners,…)
n Local area networks (LAN)
n Integrated service digital network (ISDN)
n Industrial programmable logic controllers
n High speed parallel and serial applications
n Multipoint applications with noisy environment
Typical Application
20062601
A Typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable.
Pull up and pull down resistors maybe required at the end of the bus to provide failsafe biasing. The biasing resistors provide a bias to the cable when all
drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation DS200626
www.national.com
1 page  
Electrical Characteristics (Continued)
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min Typ
VOH
CMOS High-level Output
IOH = −4mA, VID = 200mV
Voltage
3.5
VOL
IOZR
CMOS Low-level
Tristate Output Leakage
Current
IOL = 4mA, VID = −200mV
0.4V ≤ VO ≤ + 2.4V
RIN Input Resistance
Power Supply Current
− 7V ≤ VCM≤+12V
12
ICC
IOSD1
Supply Current
Driver Short-circuit Output
Current
DE = VCC, RE = GND or VCC
DE = 0V, RE = GND or VCC
VO = high, −7V ≤ VCM ≤ + 12V
(Note 8)
320
315
35
IOSD2
Driver Short-circuit Output
Current
VO = low, − 7V ≤VCM ≤ + 12V
(Note 8)
35
IOSR
Receiver Short-circuit Output 0 V ≤VO ≤ VCC
Current
7
Switching Characteristics
Driver
TPLH,
TPHL
TSKEW
Propagation Delay Input to
Output
Driver Output Skew
RL = 54Ω, CL = 100pF
(Figure 3, Figure 7)
RL = 54Ω, CL = 100 pF
(Figure 3, Figure 7)
10 35
5
TR,
TF
TZH,
TZL
THZ,
TLZ
Receiver
Driver Rise and Fall Time
Driver Enable to Ouput Valid
Time
Driver Output Disable Time
RL = 54Ω, CL = 100 pF
(Figure 3, Figure 7)
CL = 100 pF, RL = 500Ω
(Figure 4, Figure 8)
CL = 15 pF, RL = 500Ω
(Figure 4, Figure 8)
38
25
30
TPLH,
TPHL
TSKEW
Propagation Delay Input to
Output
Receiver Output Skew
RL = 54Ω, CL = 100 pF
(Figure 5, Figure 7)
RL = 54Ω, CL = 100 pF
(Figure 5, Figure 7)
20 50
5
TZH,
TZL
Receiver Enable Time
Receiver Disable Time
CL = 15 pF, RL = 1 kΩ
(Figure 6, Figure 10)
20
20
FMAX
Maximum Data Rate
2.5
Max
0.40
±1
500
400
250
250
95
60
10
40
70
70
200
50
50
Units
V
V
µA
kΩ
µA
mA
mA
mA
nS
nS
nS
nS
nS
nS
nS
nS
nS
Mbps
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD =
(TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ.
Note 5: Voltage limits apply to DI, DE, RE pins.
Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B.
Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels.
Note 8: Peak current
5 www.national.com
5 Page 
Application Information
POWER LINE NOISE FILTERING
A factor to consider in designing power and ground is noise
filtering. A noise filtering circuit is designed to prevent noise
generated by the integrated circuit (IC) as well as noise
entering the IC from other devices. A common filtering
method is to place by-pass capacitors (Cbp) between the
power and ground lines.
Placing a by-pass capacitor (Cbp) with the correct value at
the proper location solves many power supply noise prob-
lems. Choosing the correct capacitor value is based upon
the desired noise filtering range. Since capacitors are not
ideal, they may act more like inductors or resistors over a
specific frequency range. Thus, many times two by-pass
capacitors may be used to filter a wider bandwidth of noise.
It is highly recommended to place a larger capacitor, such as
10µF, between the power supply pin and ground to filter out
low frequencies and a 0.1µF to filter out high frequencies.
By-pass capacitors must be mounted as close as possible to
the IC to be effective. Long leads produce higher impedance
at higher frequencies due to stray inductance. Thus, this will
reduce the by-pass capacitor’s effectiveness. Surface
mounted chip capacitors are the best solution because they
have lower inductance.
20062622
FIGURE 11. Placement of by-pass Capacitors, Cbp
11 www.national.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet LMS485IM.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LMS485IM | 5V Low Power RS-485 / RS-422 Differential Bus | National Semiconductor |
| LMS485IMX | 5V Low Power RS-485 / RS-422 Differential Bus | National Semiconductor |
| LMS485INA | 5V Low Power RS-485 / RS-422 Differential Bus | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |