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PDF LMC1992 Data sheet ( Hoja de datos )
| Número de pieza | LMC1992 | |
| Descripción | LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel Input-Selector | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 1994
LMC1992 Digitally-Controlled Stereo Tone and Volume
Circuit with Four-Channel Input-Selector
General Description
The LMC1992 is a monolithic integrated circuit that provides
four stereo inputs bass and treble tone controls and vol-
ume balance and front-rear fader controls These functions
are digitally controlled through a three-wire communication
interface All of the LMC1992s functions are achieved with
only three external capacitors per channel It is designed for
line level input signals (300 mV b 2V) and has a maximum
gain of 0 dB
The internal design is optimized for external capacitors hav-
ing values of 0 1 mF or less This allows the use of chip
capacitors for coupling and tone control functions
Low noise and distortion result from using analog switches
and thin-film silicon-chromium resistor networks in the sig-
nal path
Volume and fader are at minimum and tone controls are flat
when supply voltage is first applied
Additional tone control can be achieved using the LMC835
stereo 7-band graphic equalizer connected to the
LMC1992’s select-out select-in external processor loop
Features
Y Low noise and distortion
Y Four stereo inputs
Y 40 volume levels including mute
Y 20 fader levels
Y All attenuators have a 2 dB of attenuation per step
Y Front back fade control
Y External processor loop
Y Only three external components per channel
Y Serial programmable standard MICROWIRETM
interface
Y Single supply operation 6V to 12V supply voltage
Y Protection address (similar to DS8906)
Y DC-coupled inputs
Y Single supply operation
Applications
Y Automotive audio systems
Y Sound reinforcement systems
Y Home entertainment stereo television and music re-
production systems
Y Electronic music (MIDI)
Block and Connection Diagrams
Left channel shown Pin numbers in parentheses are for the right channel
TL H 10789 – 1
TL H 10789 – 2
Order Number LMC1992CCN
See NS Package Number N28B
DNR is a registered trademark of National Semiconductor Corporation
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 10789
RRD-B30M75 Printed in U S A
1 page  
Typical Performance Characteristics (Continued)
Tone Control Response
with Equal Bass and
Treble Control Settings
Tone Control Response
with Reciprocal Bass and
Treble Control Settings
Treble Tone Control
Response
TL H 10789–12
Bass Tone Control
Response
TL H 10789 – 13
Select In Impedance
vs Frequency
TL H 10789 – 14
Connection Diagram
TL H 10789 – 15
TL H 10789 – 16
TL H 10789 – 17
5
5 Page 
Applications Information (Continued)
DATA TRANSFER EXAMPLE
The following routines based on the flowchart shown in Fig-
ure 6 are examples of COPSTM microcontroller instruction
code that can be used to control the LMC1992 (see Nation-
al Semiconductor’s COPS Microcontrollers Databook for
more information) These routines arbitrarily select COPS
register 0 for I O purposes When these routines are en-
tered it is assumed that chip select is high SK (clock) is
low and SO (data) is low These routines exit with chip se-
lect high and SK and SO low Output port G0 is arbitrarily
chosen to send the chip select signal to the LMC1992
The 11 data bits needed to control the LMC1992 are as-
sumed to be in the 4-bit registers 13–15 with the 4 MSBs
in register 13 With this configuration there is an extra bit for
a data stream that is 12 bits long As previously mentioned
there can be any number of extra bits between the device
address and the function address
DATA TRANSFER ROUTINE 1
This general purpose routine handles all the overhead ex-
cept loading data into registers 13–15 It sends the data
according to the conditions discussed above The data will
be lost at the conclusion of the routine This routine con-
sumes only 17 ROM memory locations
OUT1
SEND
LBI 0 13
SC
OGI 14
LEI 8
LD
XAS
XIS
JP SEND
RC
OGI 15
LEI 0
RET
POINT TO START OF DATA
WORD
SET C TO ENABLE SK CLOCK
SELECT EXTERNAL DEVICE G0
40
ENABLE SHIFT REGISTER
OUTPUT
DATA TRANSMISSION LOOP
TURN-ON CLOCK
DE-SELECT EXTERNAL
DEVICE
SET S0 TO 0
DATA TRANSFER ROUTINE 2
This routine performs the same function as routine 1 while
preserving the contents of the data registers This routine
takes only 21 ROM memory locations
OUT1
SEND1
SEND2
LBI 0 13 POINT TO START OF DATA
WORD
SC SET C TO ENABLE SK CLOCK
OGI 14
SELECT EXTERNAL DEVICE
GO 40
LEI 8
ENABLE SHIFT REGISTER
OUTPUT
JP SEND2
XAS
LD DATA TRANSMISSION LOOP
XIS TURN-ON CLOCK
JP SEND1
XAS SEND LAST DATA
RC WAIT 4 CYCLES - DATA
GOING OUT
CLRA
NOP
XAS TURN SK CLOCK OFF
OGI 15
DE-SELECT DEVICE
LEI 0
SET S0 TO 0
RET
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LMC1992.PDF ] | |
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