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PDF LM9830 Data sheet ( Hoja de datos )
| Número de pieza | LM9830 | |
| Descripción | LM9830 36-Bit Color Document Scanner | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1998
N
LM9830 36-Bit Color Document Scanner
General Description
The LM9830 is a complete document scanner system on a sin-
gle IC. The LM9830 provides all the functions (CCD control, illu-
mination control, analog front end, pixel processing function
image data buffer/SRAM controller, microstepping motor control-
ler, and EPP parallel port interface) necessary to create a high
performance color scanner. The LM9830 scans images in 36 bit
color, and has output data formats for 36 bits, 30 bits, and 24
bits.
The only additional active components required are an external
SRAM for data buffering and power transistors for the stepper
motor. Parallel port pass-through requires two additional
TTL/CMOS logic ICs.
Applications
• Color Flatbed Document Scanners
• Color Sheetfed Document Scanners
Features
• Scans at up to 6Mpixels/s (2M RGB pixels/sec).
• Digital Pixel Processing provides 300, 200, 150, 100, 75, and
50 dpi horizontal resolution from 300dpi sensor, and 600, 400,
300, 200, 150, 100, 75, and 50 dpi horizontal resolution from
a 600dpi sensor.
• Provides 50-600dpi vertical resolution in 1 dpi increments.
• Pixel rate error correction for gain (shading) and offset errors.
• Output formats include 12 bit linear, 10 bit linear with shading
and offset, or 8 bit gamma corrected, all with 12 bit accuracy.
• Multiple CCD clocking rates allows matching of CCD clock to
scan resolution and pixel depth for maximum scan speed.
• Stepper motor control tightly coupled with buffer management
to maximize data transfer efficiency.
• PWM stepper motor current control allows microstepping for
the price of fullstepping.
• Supports 64k, 128k, or 256k x8 external SRAMs.
• Parallel Port interface supports EPP, PS2 (bidirectional), or
SPP (nibble) modes of operation.
• Pixel depths of 1, 2, or 4 bits are packed into bytes for faster
scans of line art and low pixel depth images.
• Supports 1 and 3 channel CIS and CCD devices.
• 3 (R, G, and B) user-programmable gamma correction tables.
• Able to transmit an arbitrary range of pixels to speed up
scanning of smaller items (business cards, etc.) by zooming
in on a subset of CCD pixels.
• Compatible with a wide range of color linear CCDs and
Contact Image Sensors (CIS)
• Internal bandgap voltage reference.
• 100 pin TQFP package
Key Specifications
• Analog to Digital Converter Resolution
12 Bits
• Maximum Pixel Conversion Rate
6MHz
• A4 Color 150dpi scan (typical, EPP Interface) <10 seconds
• A4 Color 300dpi scan (typical, EPP Interface) <40 seconds
• A4 Color 600dpi scan (typical, EPP Interface) <160 seconds
• Supply Voltage
+5V±10%
• Power Dissipation (typical)
350mW
Scanner Block Diagram
To
Computer
Buffer
982
To
Printer
+24V
Stepper
Motor
CCD/CIS
1-3
2-6 LM9830VJD
Illumination
1-3
28 SRAM
Power
Transistors
Ordering Information
Commercial (0°C ≤ TA ≤ +70°C)
Package
LM9830VJD
VJD100A 100 Pin Thin Quad Flatpac
LM9830VJDX
VJD100A 100 Pin Thin Quad Flatpac, Tape & Reel
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
©1998 National Semiconductor Corporation
1
http://www.national.com
1 page  
AC Electrical Characteristics
The following specifications apply for AGND=DGND=DGNDI/O=DGNDSRAM=0V, VA=VD=VDI/O=VSRAM=+5.0VDC,
fCRYSTAL IN= 50MHz, MCLK DIVIDER = 1.0 (unless otherwise noted), fMCLK = fCRYSTAL IN/MCLK DIVIDER, fADC CLK = fMCLK/8,
CL (databus loading) = 20pF/pin. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
Parallel Port 8 Bit Data Read (Figure 3)
tAF-B3
AUTOFEED falling to BUSY rising
tEPP ACCESS D0-D7 valid before BUSY rising
tB-AF2
BUSY rising to AUTOFEED rising
All Except Dataport
Dataport
(Note 14)
tEPP HOLD AUTOFEED rising to D0-D7 Tri-State
25
1.5 tADC CLK
7
1
20
45
3 tADC CLK
-5
10
10
27
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (max)
tAF-B4
AUTOFEED rising to BUSY falling
Nibble Data Read (Figure 4)
3 tMCLK
4 tMCLK
ns (max)
tAF-B3
AUTOFEED falling to BUSY rising
tNIB ACCESS1 D4-D7 valid before BUSY rising
tB-AF2
BUSY rising to AUTOFEED rising
tNIB ACCESS2 D0-D3 valid after AUTOFEED rising
tAF-B4
AUTOFEED rising edge to BUSY
falling
All Except Dataport
Dataport
25
1.5 tADC CLK
2
1
5
45
3 tADC CLK
-20
10
15
3 tMCLK
4 tMCLK
ns (max)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
Microprocessor Mode (Figures 5, 6, and 7)
tALE SETUP
D0-D7 (Address) valid before ALE
falling
0 6 ns (min)
tALE HOLD
D0-D7 (Address) valid after ALE
falling
2 8 ns (min)
tALE
tALE-R/W
ALE high time
ALE falling to CS/RD/WR falling (next
operation)
2 8 ns (min)
16 ns (min)
tWR SETUP D0-D7 valid before WR rising
tWR HOLD D0-D7 valid after WR rising
tWR WR pulse width
tRD ACCESS RD low to D0-D7 valid
tRD TRI-STATE RD high to D0-D7 Tri-State
0 6 ns (min)
2 10 ns (min)
3 10 ns (min)
22 31 ns (max)
20 28 ns (max)
5 http://www.national.com
5 Page 
Pin Descriptions
CCD Driver Signals
ø1
ø2
RS
CP1
CP2
TR1, TR2
Digital Output. CCD/CIS clock signal, phase
1.
Digital Output. CCD clock signal, phase 2.
Digital Output. Reset pulse for the CCD.
Digital Output. Clamp pulse for the CCD.
Digital Output. Clamp pulse for the CCD.
Digital Outputs. Transfer pulses for the
CCD(CIS).
Analog I/O
OSR, OSG,
OSB
Analog Inputs. These inputs (for Red, Green,
and Blue) should be tied to the sensor’s out-
put signal through DC blocking capacitors.
VREF LO FORCE,
VREF LO SENSE
Analog Output/Input. Connect VREF LO OUT to
VREF LO IN and bypass to AGND with a 0.05µF
monolithic capacitor.
VREF MID FORCE, Analog Output/Input. Connect VREF MID OUT
VREF MID SENSE
to VREF MID IN and bypass to AGND with a
0.05µF monolithic capacitor.
VREF HI FORCE,
VREF HI SENSE
Analog Output/Input. Connect VREF HI OUT to
VREF HI IN and bypass to AGND with a 0.05µF
monolithic capacitor.
VBANDGAP
Analog Output. Bypass to AGND with a
0.05µF monolithic capacitor.
General Digital I/O
CRYSTAL IN
Digital Input. This is the 50MHz (typical) mas-
ter system clock.
CRYSTAL OUT Digital Output. Used with CRYSTAL IN and an
external crystal to form a crystal oscillator.
CLK_SEL
Digital Input. Should be tied to DGND for
operation with an external crystal. To use an
external TTL or CMOS clock source, tie
CLK_SEL to VD I/O and drive the clock into the
CRYSTAL OUT pin.
PC I/O
D0 (LSB) -D7
(MSB)
STROBE
AUTOFEED
SELECTIN
INIT
ACK
BUSY
PE
SELECT
ERROR
Digital Inputs/Outputs. This is the 8 bit data
path between the LM9830 and the host com-
puter.
Digital Input. WR signal in µP Mode.
Digital Input. RD signal in µP Mode.
Digital Input. ALE signal in µP Mode.
Digital Input. CS signal in µP Mode.
Digital Output.
Digital Output.
Digital Output.
Digital Output.
Digital Output.
Printer Passthrough
TRISTATE
LATCH
Digital Output. Low when in printer
passthrough mode, high when the LM9830 is
active. Low when no power is applied to the
LM9830.
Digital Output. High when in printer
passthrough mode, low when the LM9830 is
active. Tri-state when no power is applied to
the LM9830.
Stepper Motor I/O
A, B, A, B
SENSEA,
SENSEB
SENSEGND
Digital Outputs. Pulses to stepper motor.
Analog Inputs. Current sensing for PWM
winding current control.
Analog Input. Ground sense input for PWM
winding current control.
Scanner Support I/O
PSense #1,
PSense #2
Digital Inputs. Programmable, used for sens-
ing paper, front panel switches, etc.
Misc I/O #1,
Misc I/O #2
Digital Inputs/Outputs. Programmable, used
for front panel switches, status LEDs, etc.
LAMPR,
Digital Outputs. Used to control R, G, and B
LAMPG, LAMPB LEDs of single output CIS, as well as bright-
ness of CCFL.
External RAM I/O
DB0 (LSB) -
DB7 (MSB)
A0-A17
RD
WR
Digital Inputs/Outputs. This is the 8 bit data
path between the external RAM and the
LM9830.
Digital Outputs. Address pins for up to 256k
bytes external RAM.
Digital Output. Read signal to external RAM.
Digital Output. Write signal to external RAM.
Communication Mode
CMODE
Digital Input. Tie to DGND to operate in paral-
lel port mode, or to VD I/O to operate in micro-
processor compatible mode.
Test
TEST
Analog Output. This pin can be used to view
the Sample Signal, Sample Reference, and
Clamp Signals.
Analog Power Supplies
VA
AGND
This is the positive supply pin for the analog
supply. It should be connected to a voltage
source of +5V and bypassed to AGND with a
0.1µF monolithic capacitor in parallel with a
10µF tantalum capacitor.
This is the ground return for the analog sup-
ply.
11 http://www.national.com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LM9830.PDF ] | |
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