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PDF LM9812CCV Data sheet ( Hoja de datos )
| Número de pieza | LM9812CCV | |
| Descripción | LM9812 30-Bit Color Linear CCD Sensor Processor | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 1997
N
LM9812 30-Bit Color Linear CCD Sensor Processor
General Description
The LM9812 is a high performance integrated signal proces-
sor/digitizer for color linear CCD image scanners. The LM9812
performs all the signal processing (correlated double sampling,
pixel rate offset and shading correction, color balance control,
and 10-bit analog-to-digital conversion) necessary to maximize
the performance of a wide range of linear CCD sensors.
The LM9812 can be digitally programmed to work with a wide
variety of CCDs from different manufacturers, including both 3
output RGB and 2 output GRGB CCDs. An internal Configura-
tion Register sets CCD and sampling timing to maximize perfor-
mance, simplifying the design and manufacturing processes. For
complementary voltage reference see the LM4041-ADJ.
Applications
• Color Flatbed Document Scanners
• Color Sheetfed Scanners
• Multifunction Imaging Products
• Digital Copiers
• General Purpose Linear CCD Imaging
Connection Diagrams
Features
• 6 million pixels/s conversion rate (2MHz/channel x 3)
• Pixel rate shading (gain) correction for individual pixels
eliminates errors from PRNU, illumination, etc.
• Digitally programmed color balance controls
• Pixel rate offset correction for highest quality in dark regions
• Correlated Double Sampling for lowest noise
• Reference and signal sampling points digitally controlled in
20ns increments
• 2x and 4x analog fast preview/low resolution modes
• Digital control of CCD integration time
• Generates all necessary CCD clock signals
• Compatible with a wide range of color linear CCDs and
Contact Image Sensors (CIS)
• TTL/CMOS input/output compatible
Key Specifications
• Output Data Resolution
• Pixel Conversion Rate (total)
• Supply Voltage
• Supply Voltage (Digital I/O)
• Power Dissipation (typical)
10 Bits
6MHz
+5V±5%
+3.3V±10% or +5V±5%
390mW
TR2
TR1
RS
ø2
ø1
RUN/STOP
SYNC
CS
RD
WR
MCLK
OCLK
GCLK
7 6 5 4 3 2 1 52 51 50 49 48 47
8 46
9 45
10 44
11 43
12 42
13 41
14 LM9812CCV 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
D9
D8
D7
D6
D5
VDI/O
D4
DGNDI/O
D3
D2
D1
D0
RD PIXEL
Ordering Information
Commercial (0°C ≤ TA ≤ +70°C)
Package
LM9812CCV
V52A 52 Pin Plastic Leaded Chip Carrier
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
©1997 National Semiconductor Corporation
1
http://www.national.com
1 page  
DC and Logic Electrical Characteristics (Continued)
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=+5.0VDC, VDI/O=+5.0 or +3.3VDC, VREF IN = +2.0VDC,
fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical Limits
Units
(Note 9) (Note 10) (Limits)
IDI/O
Digital I/O Supply Current
Operating, VDI/O=5.0V
Standby, VDI/O= 5.0V
Operating, VDI/O=3.3V
Standby, VDI/O= 3.3V
12 30 mA (max)
5 20 mA (max)
2 10 mA (max)
0.3 3 mA (max)
AC Electrical Characteristics, MCLK Independent
The following specifications apply for AGND=DGND=DGNDI/O=0V, VA=VD=VDI/O=+5.0VDC, VREF IN = +2.0VDC, fMCLK=24MHz,
tMCLK=1/fMCLK, tr=tf=5ns, Rs=25¾, CL (databus loading) = 50pF/pin.
Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
fMCLK
Maximum MCLK Frequency
Minimum MCLK Frequency
24 MHz (min)
4 MHz (max)
MCLK Duty Cycle
40 % (min)
60 % (max)
tSETUP (OUT)
Coefficient Data valid before latching
edge of OCLK or GCLK
GCLK and OCLK as
outputs
12
20 ns (min)
tHOLD (OUT)
Coefficient Data held after latching
edge of OCLK or GCLK
GCLK and OCLK as
outputs
-10
0 ns (min)
tSETUP (IN)
Coefficient Data Valid before latching GCLK and OCLK as
edge of OCLK or GCLK
inputs
0
5 ns (min)
tHOLD (IN)
Coefficient Data held after latching
edge of OCLK or GCLK
GCLK and OCLK as
inputs
0
5 ns (min)
tGCLK-EOC
Rising edge of GLCK to falling edge
of EOC (GCLK as output)
2 ns
tGCLK-OCLK
Rising edge of GLCK to falling edge
of OCLK (GCLK and OCLK as
outputs)
2 bus / 2 clock mode
1
ns
tEOC-OCLK Rising edge of EOC to rising edge of 2 clock mode
OLCK (OCLK as output)
1
ns
tOCLK-GCLK
Rising edge of OLCK to falling edge
of GLCK (GCLK and OCLK as
outputs)
2 clock mode
3
ns
tEOC-GCLK
Rising edge of EOC to falling edge of
GLCK (GCLK as output)
2 bus mode
2
ns
tDACC
RD or RD_PIXEL low to D0-D9 data
valid
15 41 ns (max)
tD1H, D0H
RD or RD_PIXEL high to D0-D9 data
tri-state
13 20 ns (max)
tCS SETUP
tCS HOLD
tWR SETUP
CS setup of RD or WR
CS hold after RD or WR
D0-D9 data valid before rising edge
of WR (setup time)
0 ns (min)
0 ns (min)
5 ns (min)
5 http://www.national.com
5 Page 
Timing Diagrams
RUN/STOP
SYNC (OUTPUT)
Ø1
Line 1
Line 2
Diagram 1: SYNC OUT Mode Timing, Multiple Lines
Line n
SYNC (INPUT)
Ø1
Line 1
Line 2
Diagram 2: SYNC IN Mode Timing, Multiple Lines
Line n
(truncated)
RUN/
STOP
SYNC
(OUTPUT)
Transfer Dummy Black
Ø1
Valid Pixels
Additional Integration Time
TR1
RS
CLAMP
123
OCLK
GLCK
EOC
Diagram 3: SYNC OUT Mode Timing, One Line
11 http://www.national.com
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| PDF Descargar | [ Datasheet LM9812CCV.PDF ] | |
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