PDF K4D26323RA Data sheet ( Hoja de datos )

Número de pieza	K4D26323RA
Descripción	1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
Fabricantes	Samsung
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No Preview Available ! K4D26323RA-GC * VDD / VDDQ=2.8V * 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 2.0 January 2003 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 2.0 (Jan. 2003) 1 page K4D26323RA-GC * VDD / VDDQ=2.8V * PIN CONFIGURATION (Top View) 128M DDR SDRAM 2 3 4 5 6 7 8 9 10 11 12 13 B DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3 C DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 F DQ17 DQ16 VDDQ VSSQ VSS VSS VSS VSS Thermal Thermal Thermal Thermal VSSQ VDDQ DQ15 DQ14 G DQ19 DQ18 VDDQ VSSQ VSS VSS VSS VSS Thermal Thermal Thermal Thermal VSSQ VDDQ DQ13 DQ12 H DQS2 DM2 NC VSSQ VSS VSS VSS VSS Thermal Thermal Thermal Thermal VSSQ NC DM1 DQS1 J DQ21 DQ20 VDDQ VSSQ VSS VSS VSS VSS Thermal Thermal Thermal Thermal VSSQ VDDQ DQ11 DQ10 K DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 L CAS WE VDD VSS A10 VDD VDD RFU1 VSS VDD NC NC M RAS NC NC BA1 A2 A11 A9 A5 RFU2 CK CK MCL N CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional PIN DESCRIPTION CK,CK CKE CS RAS CAS WE DQS DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~A11 DQ0 ~ DQ31 VDD VSS VDDQ VSSQ NC MCL -5- Bank Select Address Address Input Data Input/Output Power Ground Power for DQ’s Ground for DQ’s No Connection Must Connect Low Rev. 2.0 (Jan. 2003) 5 Page K4D26323RA-GC * VDD / VDDQ=2.8V * 128M DDR SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 Storage temperature TSTG -55 ~ +150 Power dissipation PD 3.3 Short circuit current IOS 50 Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Unit V V V °C W mA POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Device Supply voltage Output Supply voltage Symbol VDD VDDQ Min 2.66 2.66 Typ Max 2.8 2.94 2.8 2.94 Reference voltage VREF 0.49VDDQ - 0.51VDDQ Termination voltage Input logic high voltage Vtt VIH(DC) VREF-0.04 VREF+0.15 VREF - VREF+0.04 VDDQ+0.30 Input logic low voltage Output logic high voltage VIL(DC) VOH -0.30 Vtt+0.76 - VREF-0.15 -- Output logic low voltage VOL - Input leakage current IIL -5 Output leakage current IOL -5 - Vtt-0.76 -5 -5 Unit V V V V V V V V uA uA Note 1,7 1,7 2 3 4 5 IOH=-15.2mA IOL=+15.2mA 6 6 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. For K4D26323RA-GC2A/33/36, VDD/VDDQ=2.8V + 5% - 11 - Rev. 2.0 (Jan. 2003) 11 Page

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