PDF HYS72D128020GR-7-B Data sheet ( Hoja de datos )

Número de pieza	HYS72D128020GR-7-B
Descripción	2.5 V 184-pin Registered DDR-I SDRAM Modules
Fabricantes	Infineon
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No Preview Available ! HYS 72Dxx0xxGR-7/8-B Registered DDR-I SDRAM-Modules 2.5 V 184-pin Registered DDR-I SDRAM Modules 256MB, 512MB &1GByte Modules PC1600 & PC2100 Preliminary Datasheet revision 0.91 • 184-pin Registered 8-Byte Dual-In-Line DDR-I SDRAM Module for PC and Server main memory applications • One bank 32M × 72, 64M x 72, and two bank 64M x 72 and 128M × 72 organization • JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) with a single + 2.5 V (± 0.2 V) power supply • Built with 256Mbit DDR-I SDRAMs in 66- Lead TSOPII package • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • All inputs and outputs SSTL_2 compatible • Re-drive for all input signals using register and PLL devices. • Serial Presence Detect with E2PROM • Jedec standard MO-206 form factor: 133.35 mm (nom.) × 43.18 mm (nom.) × 4.00 mm (max.) (6,80 mm max. with stacked components) • Jedec standard reference layout: Raw Cards A, B and C • Gold plated contacts • Performance: -7 -8 Unit Component Speed Grade DDR266A DDR200 Module Speed Grade PC2100 PC1600 fCK Clock Frequency (max.) @ CL = 2.5 143 125 MHz fCK Clock Frequency (max.) @ CL = 2 133 100 MHz Description The HYS 72Dxx0x0GR are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies 1 2002-09-10 (revision 0.91) 1 page HYS 72Dxx0xxGR-7/8-B Registered DDR-I SDRAM-Modules RS0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQS8 DQ31 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D8 DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D4 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Serial PD DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D7 VDDSPD SCL A0 A1 A2 SA0 SA1 SA2 SDA VDD, VDDQ VREF V SS V DDID EEPROM D0 - D8 D0 - D8 D0 - D8 D0 - D8 Strap: see Note 4 CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R RS0 -> CS : SDRAMs D0-D8 E RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8 G RA0-RA12 -> A0-A12: SDRAMs D0 - D8 I RRAS -> RAS : SDRAMs D0 - D8 S T RCAS -> CAS : SDRAMs D0 - D8 E RCKE0 -> CKE: SDRAMs D0 - D8 R RWE -> WE : SDRAMs D0 - D8 RESET CK0, CK 0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM. Block Diagram: One Bank 32Mb x 72 DDR-I SDRAM DIMM Module HYS72D32000GR using x8 organized SDRAMs on Raw Card Version A INFINEON Technologies 5 2002-09-10 (revision 0.91) 5 Page HYS 72Dxx0xxGR-7/8-B Registered DDR-I SDRAM-Modules Operating, Standby and Refresh Currents (PC2100) Symbol Parameter/Condition 256MB x72 1bank -7 MAX 512MB x72 1bank -7 MAX 512MB x72 2bank -7 MAX 1GB x72 2bank -7 MAX Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK IDD0 MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 900 1800 1395 2790 Unit Notes 5 mA 1, 4 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. 990 1980 1485 2970 mA 1, 3, 4 Precharge Power-Down Standby Current: all banks idle; power-down IDD2P mode; CKE <= VIL MAX; tCK = tCK MIN 72 144 144 288 mA 2, 4 Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE IDD2F >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once 360 720 720 1440 mA 2, 4 per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; IDD2Q CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at 225 450 450 900 mA 2, 4 >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; IDD3P CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. 162 324 324 648 mA 2, 4 Active Standby Current: one bank active; active / precharge;CS >= VIH IDD3N MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 495 IDD4R Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA 1035 IDD4W Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN 1125 IDD5 IDD6 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 1620 27,0 IDD7 Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 2025 990 2070 2250 3240 54 4050 990 1530 1620 2115 54 2520 1980 3060 3240 4230 108 5040 mA 2, 4 mA 1, 3, 4 mA 1, 4 mA 1, 4 mA 2, 4 mA 1, 3, 4 1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents 5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C INFINEON Technologies 11 2002-09-10 (revision 0.91) 11 Page

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