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PDF UPA1755 Data sheet ( Hoja de datos )
| Número de pieza | UPA1755 | |
| Descripción | SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µPA1755
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
This product is Dual N-channel MOS Field Effect
Transistor designed for DC/DC converters and power
management applications of notebook computers.
FEATURES
• Dual chip type
• Low on-resistance
RDS(on)1 = 32 mΩ MAX. (VGS = 10 V, ID = 3.5 A)
RDS(on)2 = 45 mΩ MAX. (VGS = 4.5 V, ID = 3.5 A)
• Low input capacitance Ciss = 895 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PACKAGE DRAWING (Unit : mm)
85
14
5.37 Max.
1 ; Source 1
2 ; Gate 1
7, 8 ; Drain 1
3 ; Source 2
4 ; Gate 2
5, 6 ; Drain 2
6.0 ±0.3
4.4
0.8
1.27 0.78 Max.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
PART NUMBER
µPA1755G
PACKAGE
Power SOP8
EQUIVALENT CIRCUIT
(1/2 Circuit)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, All terminals are connected.)
Drain to Source Voltage (VGS = 0)
VDSS 30 V
Gate to Source Voltage (VDS = 0)
VGSS ±20 V
Drain Current (DC)
Drain Current (pulse) Note1
Total Power Dissipation (1 unit) Note2
Total Power Dissipation (2 unit) Note2
ID(DC)
ID(pulse)
PT
PT
±7.0
±28
1.7
2.0
A
A
W
W
Channel Temperature
Tch 150 °C
Storage Temperature
Tstg –55 to + 150 °C
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1 %
2. TA = 25 °C, Mounted on ceramic substrate of 2000 mm2 x 1.1 mm
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G12715EJ1V0DS00 (1st edition)
Date Published March 1999 NS CP(K)
Printed in Japan
©
1998
1 page  
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100 Mounted on ceramic
substrate of
10
1
RD(VS(GonS)
=Li1m0itVe)d
ID(DC)
TA = 25 ˚C
ID(pulse) = 28 A 2000mm2×1.1mm,
P
=7A
Power
W=1
P
P W = 10 ms
DissipatWio=n1L0i0mmitesd
ms
1
unit
0.1 Single Pulse
0.1 1
10 100
VDS - Drain to Source Voltage - V
FORWARD TRANSFER CHARACTERISTICS
100 Pulsed
10
1 TA=150˚C
TA=125˚C
TA=75˚C
0.1
TA=25˚C
TA=−25˚C
TA=−50˚C
VDS = 10 V
12345
VGS - Gate to Source Voltage - V
µPA1755
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
Mounted on ceramic
substrate of
2.4 2000mm2×1.1mm
2 unit
2.0
1 unit
1.6
1.2
0.8
0.4
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
20 VGS=10 V
Pulsed
VGS=4.5 V
VGS=4 V
10
0 0.2 0.4 0.6 0.8
VDS - Drain to Source Voltage - V
Data Sheet G12715EJ1V0DS00
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPA1755.PDF ] | |
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