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PDF PTN3500D Data sheet ( Hoja de datos )

Número de pieza PTN3500D
Descripción Maintenance and control device
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
PTN3500
Maintenance and control device
Product specification
Supersedes data of 2000 Nov 22
2001 Jan 17
Philips
Semiconductors

1 page




PTN3500D pdf
Philips Semiconductors
Maintenance and control device
Product specification
PTN3500
Addressing
For addressing, see Figure 8.
SLAVE ADDRESS
SLAVE ADDRESS
S 0 1 0 0 A2 A1 A0 0 A
S 1 0 1 0 A2 A1 A0 0 A
(a) I/O EXPANDER
(b) MEMORY
a. b.
Figure 8. PTN3500 slave addresses
SW00547
Asynchronous Start
Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The
device does not support a Stop or a repeated Start condition during this time period.
I/O OPERATIONS (see also Figure 7)
Each of the PTN3500’s eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port to the
microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9).
SCL
12 345 678
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
SDA S 0 1 0 0 A2 A1 A0 0 A
DATA 1
START CONDITION
WRITE TO
PORT
R/W ACKNOWLEDGE
FROM SLAVE
DATA TO PORT
A DATA 2
ACKNOWLEDGE
FROM SLAVE
A
ACKNOWLEDGE
FROM SLAVE
DATA OUT
FROM PORT
t pv
Figure 9. I/O WRITE mode (output)
DATA 1 VALID
t pv
DATA 2 VALID
SW00548
SLAVE ADDRESS (I/O EXPANDER)
DATA FROM PORT
SDA
S 0 1 0 0 A2 A1 A0 1 A
DATA 1
READ FROM
PORT
START CONDITION
R/W ACKNOWLEDGE
FROM SLAVE
DATA FROM PORT
A DATA 4
ACKNOWLEDGE
FROM MASTER
DATA INTO
PORT
DATA 1
DATA 2
t ph
DATA 3
t ps
DATA 4
Figure 10. I/O READ mode (input)
1P
STOP
CONDITION
SW00549
2001 Jan 17
5

5 Page





PTN3500D arduino
Philips Semiconductors
Maintenance and control device
Product specification
PTN3500
POWER-UP TIMING
SYMBOL
PARAMETER
MAX.
UNIT
tPUR1
Power-up to Read Operation
1 ms
tPUW1
Power-up to Write Operation
5 ms
NOTE:
1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
WRITE CYCLE LIMITS
SYMBOL
PARAMETER
MIN.
tWR1
Write Cycle Time
NOTE:
1. tWR is the maximum time that the device requires to perform the internal write operation.
Write Cycle Timing
TYP. (5)
5
MAX.
10
UNIT
ms
SCL
SDA
8th Bit
Word n
ACK
Stop
Condition
Figure 18.
tWR
Start
Condition
MEMORY
ADDRESS
SW00560
2001 Jan 17
11

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