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PDF SL74HC323N Data sheet ( Hoja de datos )
| Número de pieza | SL74HC323N | |
| Descripción | 8-Bit Bidirectional Universal Shift Register with Parallel I/O | |
| Fabricantes | System Logic Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SL74HC323N (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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SL74HC323
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Performance Silicon-Gate CMOS
The SL74HC323 is identical in pinout to the LS/ALS323. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC323 features a multiplexed parallel input/output data
port to active full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally
suited for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both Mode-
Select lines, S1 and S2, high. This places the outputs in the high-
ORDERING INFORMATION
SL74HC323N Plastic
SL74HC323D SOIC
TA = -55° to 125° C for all packages
impedance state, which permits data applied to the data port to be
clocked into the register. Reading out of the register can be
accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
PIN ASSIGNMENT
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
SLS
System Logic
Semiconductor
1 page  
SL74HC323
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
tsu
Parameter
Minimum Setup Time, Mode Select S1
or S2 to Clock (Figure 4)
tsu Minimum Setup Time, Data Inputs SA,
SH, PA thru PH to Clock
(Figure 4)
th Minimum Hold Time, Clock to Mode
Select S1 or S2 (Figure 4)
th Minimum Hold Time, Clock to Data
Inputs, SA, SH, PA thru PH (Figure 4)
tw Minimum Pulse Width, Clock (Figure
1)
tw Minimum Pulse Width, Reset (Figure
2)
tr, tf Maximum Input Rise and Fall Times
(Figure 1)
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25 °C to-55°C ≤85°C ≤125°C
100 125 150
20 25 30
17 21 26
100 125 150
20 25 30
17 21 26
120 150 180
24 30 36
20 26 31
5 55
5 55
5 55
80 100 120
16 20 24
14 17 20
80 100 120
16 20 24
14 17 20
1000 1000 1000
500 500 500
400 400 400
Unit
ns
ns
ns
ns
ns
ns
ns
SLS
System Logic
Semiconductor
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SL74HC323N.PDF ] | |
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