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PDF SL74HC175N Data sheet ( Hoja de datos )

Número de pieza SL74HC175N
Descripción Quad D Flip-Flop with Common Clock and Reset
Fabricantes System Logic Semiconductor　
Logotipo System Logic Semiconductor Logotipo



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No Preview Available ! SL74HC175N Hoja de datos, Descripción, Manual

SL74HC175
Quad D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The SL74HC175 is identical in pinout to the LS/ALS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive-going edge of the Clock input.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC175N Plastic
SL74HC175D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Reset Clock D Q Q
L X X LH
H H HL
H L LH
H L X no change
X = Don’t care
SLS
System Logic
Semiconductor

1 page




SL74HC175N pdf
SL74HC175
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor

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