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Número de pieza | TDA8785H | |
Descripción | 8-bit high-speed analog-to-digital converter with gain and offset controls | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TDA8785H (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
No Preview Available ! INTEGRATED CIRCUITS
DATA SHEET
TDA8785
8-bit high-speed analog-to-digital
converter with gain and offset
controls
Product specification
Supersedes data of 1996 Jan 17
File under Integrated Circuits, IC02
1997 Dec 18
1 page Philips Semiconductors
8-bit high-speed analog-to-digital converter
with gain and offset controls
handbook, full pagewidth
VCCA1 1
VCCA2 2
AGND1 3
AGND2 4
DEC2 5
B6
VRB 7
VDACO(n) 8
VDACO(p) 9
VFSDAC(p) 10
VFSDAC(n) 11
TDA8785
Product specification
TDA8785
33 AD7
32 AD6
31 AD5
30 AD4
29 AD3
28 AD2
27 AD1
26 AD0
25 VCCO
24 OGND
23 VCCD
MBG680
Fig.2 Pin configuration.
1997 Dec 18
5
5 Page Philips Semiconductors
8-bit high-speed analog-to-digital converter
with gain and offset controls
Product specification
TDA8785
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Timing
ADC DIGITAL OUTPUTS (CL = 15 pF)
tds sampling delay time
th output hold time
td output delay time
− 1.5 − ns
7 − − ns
− − 16 ns
DAC OUTPUTS (PINS VDACO(p) AND VDACO(n))
tSU; DAT
tHD; DAT
tS
data set-up time
data hold time
DAC setting time (10 to 90%)
RSA
residual setting accuracy
note 4
note 4
RL = 150 Ω; CL = 15 pF
note 5; see Fig.8
−0.3
−
−
−
−
8
0.1
− ns
2 ns
− ns
2.5 %
3-STATE OUTPUT DELAY TIMES (see Fig.5)
tdZH enable HIGH
tdZL enable LOW
tdHZ disable HIGH
tdLZ disable LOW
− 15 20 ns
− 15 20 ns
− 13 20 ns
− 10 20 ns
Notes
1. Vos is proportional to the amplifier gain. For instance, Vos at 20 dB is the one indicated at 0 dB multiplied by 10.
2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and
analog grounds is recommended.
3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; fclk = 30 MHz; no external
filtering on pin 6 (B).
4. The data set-up time (tSU; DAT) is the minimum period preceding the rising edge of the clock, that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (tHD; DAT) is the minimum period following the rising edge
of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.
5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling
shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour.
The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time tX.
1997 Dec 18
11
11 Page |
Páginas | Total 24 Páginas | |
PDF Descargar | [ Datasheet TDA8785H.PDF ] |
Número de pieza | Descripción | Fabricantes |
TDA8785 | 8-bit high-speed analog-to-digital converter with gain and offset controls | NXP Semiconductors |
TDA8785H | 8-bit high-speed analog-to-digital converter with gain and offset controls | NXP Semiconductors |
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