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PDF TLE7230G Data sheet ( Hoja de datos )
| Número de pieza | TLE7230G | |
| Descripción | Smart Octal Low-Side Switch | |
| Fabricantes | Infineon Technologies AG | |
| Logotipo |  |
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Target Datasheet TLE7230 R/G
Smart Octal Low-Side Switch
Features
Product Summary
♦ Full Protection
Overload
Supply voltage
VS 4.5 – 5.5 V
Overtemperature
Overvoltage
♦ Low Quiescent Current< 10µA
Drain source clamping voltage VDS(AZ)max 60
On resistance
RON 0.8
V
Ω
♦ 16 bit SPI (for Daisychain)
♦ Direct Parallel Control of Four Channels
♦ PWM input (demux)
♦ Parallel Inputs High or Low Active Programmable
♦ Programmable functions
Boollean operation
Overload behavior
Overtemperature behavior
Power P-DSO 36
Switching time
♦ General Fault Flag
♦ Digital Ports Compatible to 5V and 3,3 V Micro Controllers
♦ Electostatic Discharge (ESD) Protection
♦ Full reverse current capability without latchup or loss of function
P-DSO-24
General description
Detailed Block Diagram
Octal Low-Side Switch in
Smart Power Technology
(SPT) with a Serial Peripheral
Interface (SPI) and eight open
drain DMOS output stages.
The TLE 7230 R/G is pro-
tected by embedded protec-
tion functions and designed for
automotive applications.
IN1
IN2
IN3
IN4
SCLK
SI
CS
SO
GND
PRG
VS
RESET VS
FAULT
VDO
as Ch. 1
as Ch. 1
as Ch. 1
LOGIC
Protection
Functions
Output Stage
16
8
Serial Interface
SPI
14
Output Control
Buffer
8
GND
VBB
OUT1
OUT8
V1.1
Page 1
12. Oct. 2003
1 page  
Target Datasheet TLE7230 R/G
Electrical Characteristics
Parameter and Conditions
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
1. Power Supply, Reset
Supply Voltage1
Supply Current
Supply Current (reset mode)
Minimum Reset Duration
Reset = L
2. Outputs
ON Resistance VS = 5 V; ID = 500 mA
Output Clamping Voltage
Current Limit
TJ = 25°C
TJ = 150°C
Output OFF
Output Leakage Current
Turn-On Time
VReset = L
Vbb=12V
ID = 0.5 A, resistive load
Turn-Off Time
ID = 0.5 A, resistive load
3. Digital Inputs
Input Low Voltage
Input High Voltage
Input Voltage Hysteresis
Input Pull Down/Up Current (IN1 ... IN4)
PRG, Reset Pull Up Current
Input Pull Down Current (SI, SCLK)
Input Pull Up Current (CS)
4. Digital Outputs (SO, Fault)
SO High State Output Voltage
ISOH = 2 mA
SO Low State Output Voltage
ISOL = 2.5 mA
Output Tri-state Leakage Current CS = H, 0 ≤ VSO ≤ VS
Fault Output Low Voltage
IFAULT = 1.6 mA
Symbol Values
min typ
max
Unit
VS
4.5 --
5.5
V
IS -- 1 2 mA
IS(reset)
--
10 µA
tReset,min
10
--
--
µs
RDS(ON)
VDS(AZ)
ID(lim)
ID(lkg)
tON
tOFF
--
--
48
1
--
--
--
0.8 1
-- 1.7
-- 60
2
-- 5
Ω
V
A
µA
15 / µs
60
15 / µs
60
VINL
VINH
VINHys
IIN(1..4)
IIN(PRG,Res)
IIN(SI,SCLK)
IIN(CS)
- 0.3
2.0
-- 1.0
-- --
100
50
50
20
20
V
V
mV
µA
µA
µA
µA
VSOH
VVDO -
0.4
--
--
V
VSOL
--
-- 0.4
V
ISOlkg
-10 0 10 µA
VFAULTL
--
-- 0.4
V
1 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched
off.
V1.1
Page 5
12. Oct. 2003
5 Page 
Target Datasheet TLE7230 R/G
Register Description:
Name Nr. 7 6 5 4 3 2 1 0
MAP
BOL
OVL
OVT
SLE
STA
CTL
1 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
2 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
3 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
4 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
5 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
6 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
7 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
ADDR
001
010
011
100
101
110
111
default
08H
00H
00H
00H
00H
00H
00H
Input Mapping Rgister (MAP)
Defined to which outputs the IN4 / IN is assigned (can be one up to all)
0.. No connection to IN4 / IN
1.. Output can be controlled with IN4 / IN pin
Boolean operation Register (BOL)
The logic operation for serial and parallel control signal is defined for all channels individually
0.. Logic "OR"
1.. Logic "AND"
Overload Behavior Rgister (OVL)
The overload behavior of a single channel is defined.
0.. Current limit without shutdown of the channel
1.. Current limit with latching overload shutdown of the channel
Overtemperature Behavior Register (OVT)
The overtemperature behavior of a single channel is defined.
0.. Autorestart after cooling down
1.. Latching shutdown on overtemperature
Switching Speed / Slew Rate Register (SLE)
The switching speed of the channels is defined
0.. fast (10µs)
1.. slow (50µs)
Output State Register (STA)
Reads back the state of the output (read only register)
0: DMOS off
1: DMOS on
Serial Output Control Register (CTL)
Sets the serial controll bits for switching the output stages.
0: Output off
1: Output on
SPI Diagnostics:
As soon as a fault occurs for longer than the fault filtering time, the fault information is latched into the
diagnosis register (and the Fault pin will change from high to low state). A new error on the same
channel will over-write the old error report. Serial data out pin (SO) is in a high impedance state when
CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. If the sent com-
V1.1
Page 11
12. Oct. 2003
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TLE7230G.PDF ] | |
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