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PDF TLE6244X Data sheet ( Hoja de datos )
| Número de pieza | TLE6244X | |
| Descripción | 18 Channel Smart Lowside Switch | |
| Fabricantes | Infineon Technologies AG | |
| Logotipo |  |
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TLE 6244X
18 Channel Smart Lowside Switch
ASSP for Powertrain
Final Data Sheet
Features
• Short Circuit Protection
• Overtemperature Protection
• Overvoltage Protection
• 16 bit Serial Data Input and Diagnostic Output
(2 bit/chan. acc. SPI Protocol)
• Direct Parallel Control of 16 channels for PWM
Applications
• Low Quiescent Current
• Compatible with 3.3V Microcontrollers
• Electrostatic discharge (ESD) Protection
P-MQFM 64-10
Ordering Code: Q67007-A9613
General description
18-fold Low-Side Switch (0.35 Ω to 1 Ω) in Smart Power Technology (SPT) with a Serial Pe-
ripheral Interface (SPI) and 18 open drain DMOS output stages. The TLE6244X is protected
by embedded protection functions and designed for automotive and industrial applications.
The output stages are controlled via SPI Interface. Additionally 16 of the 18 channels can be
controlled direct in parallel for PWM applications. Therefore the TLE6244X is particularly
suitable for engine management and powertrain systems.
VS
IN1
IN2
IN15
IN16
SCLK
SI
as Ch. 1
as Ch. 1
as Ch. 1
as Ch. 1
as Ch. 1
as Ch. 1
as Ch. 1
LOGIC
16 1 16
Serial Interface
SPI
Output Control
Buffer
SO
Final Data Sheet
GND
1
Protection
Functions
Output Stage
VBB
OUT1
OUT18
V4.2, 2003-08-29
1 page  
TLE 6244X
All low side switches are equipped with fault diagnostic functions:
- short-circuit to UBatt: (SCB) can be detected if switches are turned on
- short-circuit to ground: (SCG) can be detected if switches are turned off
- open load:
(OL) can be detected if switches are turned off
- overtemperature:
(OT) will only be detected if switches are turned on
The fault conditions SCB, SCG, OL and OT will not be stored until an integrated filtering time is
expired (please note for PWM application). If, at one output, several errors occur in a sequence,
always the last detected error will be stored (with filtering time). All fault conditions are encoded
in two bits per switch and are stored in the corresponding SPI registers. Additionally there are
two central diagnostic bits: one specially for OT and one for fault occurrence at any output.
The registers can be read out via SPI. After each read out cycle the registers have to be cleared
by the DEL_DIA command.
1.3.1 Power Stage OUT8 (Condensed Description)
1.3.1.1 Control of OUT8 and VDD-Monitoring
OUT8 can be controlled by SPI or by the pin IN8 only, control by µs-bus is not possible. When
controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. In
SPI mode the power stage is fully supervised by the VDD-monitor.
If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and
not by undervoltage detection.
1.3.1.2 Phase Relation IN8 - OUT8
The phase relation IN8 -> OUT8 is inverting.
OUT8 is active if IN8 is set to logic '1' (high level, see 3.4.2 ) in case of parallel access.
On executing the read instruction on RD_INP1/2 the inverted status of IN8 is read back.
1.3.1.3 Reset / Power Stage Diagnostics
If OUT8 is controlled by IN8, OUT8 will not be reseted by RST.
After reset parallel control (by IN8) is active for OUT8.
If UVDD < 4.5V errors are not stored because of the active RST of the external Regulator. Nev-
ertheless
OUT8 is protected against overload.
1.3.1.4 Input Current
The control input IN8 has an internal pull-down current source. Thus the input currents I IN8
are positive (flow into the pin).
1.3.1.5 On Resistance
For OUT8 and 3.5V < UVDD < 4.5V R on increases (see 3.8.5).
1.3.1.6 Parallel Connection of Power Stages
Parallel connection of power stages with OUT8 and parallel control is prohibited (inverting
input IN8). Control via SPI is possible. See 1.13.
Final Data Sheet
5 V4.2, 2003-08-29
5 Page 
TLE 6244X
detected the data byte ’00h’ is transmitted to the controller after having sent the verification
byte (even if bit INSW afterwards is wrong) but modifications on any register of TLE6244 are
not allowed until bit INSW is valid, too.
If an invalid instruction is detected bit TRANS_F in the following verification byte is set to
’High’. This bit must not be cleared before it has been sent to the microcontroller.
6) If TLE6244X and additional IC’s are connected to one common slave select, they are
distinguished by the chip address (CPAD1, CPAD0). If an IC with 32bit-transmission-format is
selected, TLE6232 must not be activated, even if slave select is set to ’low’ and
the first two bits of the third byte of the 32bit-transmission are identical to the chip address
of TLE6244X.
During the transmission of CPAD1 and CPAD0 the data output SO remains in tristate (see
timing diagram of the SPI in chapter 3.9. ).
SPI access format:
WRITE-access (16bit)
8 bit command + 8bit data
SS
READ-access (16bit)
8 bit command + 8bit data
SS
SI SPI instruction
MSB
Data 8bit
MSB
SI SPI instruction
MSB
XX XX XX XX
SO
Check byte
ZZ + 6bit
00 00 00 00
SO
Z=tristate
Check byte
ZZ + 6bit
Data 8bit
MSB
Verification byte:
MSB
76543210
Z Z 1 0 1 0 1 TRANS_F
Bit Name
Description
0
TRANS_F
Bit = 1: error detected during previous transfer
Bit = 0: previous transfer was recognised as valid
State after reset: 0
1 Fixed to High
2 Fixed to Low
3 Fixed to High
4 Fixed to Low
5 Fixed to High
6 send as high impedance
7 send as high impedance
Final Data Sheet
11 V4.2, 2003-08-29
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TLE6244X.PDF ] | |
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