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PDF TMC2302AKEC1 Data sheet ( Hoja de datos )
| Número de pieza | TMC2302AKEC1 | |
| Descripción | Image Manipulation Sequencer | |
| Fabricantes | Fairchild Semiconductor | |
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TMC2302A
Image Manipulation Sequencer
40 MHz
www.fairchildsemi.com
Features
• Asynchronous loading of control parameters
• Rapid (25ns per pixel) rotation, warping, panning, and
scaling of images
• Three-dimensional image addressing capability
• General third-order polynomial transformations in two
dimensions on-chip
• Three-dimensional transformation of up to order 1.5 also
supported
• Flexible, user-configurable pixel datapath timing structure
• Static convolutional filtering of up to 16 x 16 Pixel (one-
pass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel
(three-pass) windows
• User-selectable source image subpixel resolution of
2-8 to 2-16
• Pin-compatible upgrade to TMC2302
• 24-bit (optional 36-bit) positioning precision within the
source image space, 48-bit internal precision
• Low power CMOS process
• Available in a 120-pin Plastic Pin Grid Array and 120-lead
Metric Quad Flat Pack
Applications
• High-performance video special-effects generators
• Guidance systems
• Image recognition
• Robotics
• High-precision image registration
Description
The TMC2302A, a pin-compatible replacement for the
TMC2302, is a high-speed self-sequencing address genera-
tor which supports image manipulations such as rotation,
rescaling, warping, filtering, and resampling. It remaps the
pixel locations of a target (display) space back into those of a
source image space. The degree and type of image manipula-
tion is determined by the remapping selected.
To remap from the target to the source space, this integrated
circuit computes a series of polynomials of the target space
coordinates, based on user-assigned coefficients. Two
TMC2302A chips can generate third-order warps of a two-
dimensional image, whereas three can second-order warp a
three-dimensional image.
Simplified Block Diagram
IDAT15-0
ASYNCHRONOUS IADR6-0
HOST INTERFACE ICS
IWR
SYNC
SYNCHRONOUS
HOST INTERFACE
NOOP
INIT
CLK
CONTROL
PARAMETER
REGISTERS
CONTROL
SOURCE
ADDRESS
GENERATOR
WALK
COUNTER
TARGET
ADDRESS
GENERATOR
65-2302-01
OES
SOURCE MEMORY
SADR23-0
INTERFACE
SVAL
OEK
KADR7-0
ACC
TWR
CONVOLUTIONAL
CONTROL
OET
TADR11-0
TVAL
TARGET
MEMORY
INTERFACE
END
DONE
SYNC FLAGS
Rev. 0.9.2
1 page  
PRODUCT SPECIFICATION
Pin Assignments
120 Pin Plastic Pin Grid Array, PPGA
1 2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
KEY
E
F
Top View
G Cavity Up
H
J
K
L
M
N
65-2302-05
TMC2302A
Pin Name Pin Name Pin Name
A1 GND
C5 SADR19 G11 GND
A2 SADR16 C6 SADR22 G12 VDD
A3 SADR17 C7 IADR5 G13 IDAT0
A4 VDD
C8 IADR1 H1 SADR5
A5 SADR21 C9 IDAT14 H2 SADR4
A6 OES
C10 IDAT10 H3 GND
A7 IADR6 C11 GND H11 GND
A8 IADR3 C12 GND
H12 VDD
A9 IADR0 C13 IDAT6 H13 SYNC
A10 IDAT15 D1 SADR11 J1 SADR3
A11 IDAT12 D2 SADR12 J2 SADR2
A12 IDAT9 D3 GND
J3 VDD
A13 VDD
D11 VDD
J11 VDD
B1 SADR14 D12 IDAT5 J12 CLK
B2 SADR15 D13 IDAT4 J13 IWR
B3 VDD
E1 SADR9 K1 SADR1
B4 SADR18 E2 SADR10 K2 SADR0
B5 SADR20 E3 GND
K3 GND
B6 SADR23 E11 GND
K11 VDD
B7 IADR4 E12 IDAT3 K12 INIT
B8 IADR2 E13 IDAT2 K13 GND
B9 ICS
F1 SADR7 L1 SVAL
B10 IDAT13 F2 SADR8 L2 VDD
B11 IDAT11 F3 VDD
L3 NC
B12 IDAT8 F11 VDD
L4 VDD
B13 IDAT7 F12 GND L5 GND
C1 SADR13 F13 IDAT1 L6 KADR0
C2 VDD
G1 SADR6 L7 VDD
C3 VDD
G2 GND L8 TADR4
C4 GND
G3 VDD
L9 TADR8
Pin
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Name
DONE
VDD
GND
NOOP
ACC
OEK
KADR6
KADR4
KADR2
OET
TADR0
TADR3
TADR6
TADR9
GND
GND
TVAL
GND
KADR7
KADR5
KADR3
KADR1
TWR
TADR1
TADR2
TADR5
TADR7
TADR10
TADR11
ENDD
5
5 Page 
PRODUCT SPECIFICATION
TMC2302A
Transformation Coefficient and
Configuration and Control
Parameters
The TMC2302A is intended to act as a co-processor, requir-
ing only that the user program the device to perform the
image transformation desired by loading in the appropriate
device configuration and transformation control parameters
discussed in this section. The user then issues an “Init”
command, allowing his system to run unattended until the
completion of the image when a “Done” flag is generated to
inform the host system.
The capabilities and flexibility of the TMC2302A Image
Manipulation Sequencer are apparent when reviewing the
following tables which define the transformation coefficient
and configuration and control parameters. These tables are
broken up into two separate groups. The first parameters dis-
cussed are the control words which select the dimension cal-
culated, the functional configuration of each device, the
working space in which they will operate, the size of the
interpolation kernel desired, and the timing of the various
address and control signals involved in handling the pixel
data pipeline. The second parameters are the polynomial
transform coefficients used in performing image manipula-
tion. The TMC2302A utilizes three levels of internal 48-bit
accumulators to calculate these values by forward difference
accumulation, generating no significant cumulative spatial
error for most applications. The user must be aware that all
internal parameter and coefficient registers must be set by
the user, including resetting after powerup any unused con-
trol words or coefficients.
As mentioned above, the TMC2302A also features user-
programmable image data pipeline configuration controls.
All output signals except the source and coefficient address
outputs can be individually delayed by the user up to seven
clocks after the nominal system timing illustrated in Table 4.
This allows the user to software-configure the TMC2302As
in his system to match his pixel interpolator, image buffer,
and interpolation coefficient RAM structure timing.
The user can also program the device to continue into the
next image for a set number of clock cycles after the Done
flag has appeared. First, this “flushes” the final resampled
pixel data word through the interpolation pipeline, all the
way to the target image RAM. Also, valid pixel data will
then appear on the first clock of the next transform indepen-
dent of the length of the pixel pipeline, incurring no lost
clock cycles.
Device Configuration and Control
Parameters
UMIN,
VMIN,
WMIN
The memory addresses of the target image
boundaries corresponding to the top, left side,
and front page of the new image being gener-
ated are defined in all devices of the user's
system by the parameters UMIN, VMIN, and
WMIN, respectively. At the beginning of the
transformation, the initial source image coor-
dinate (X0, Y0, Z0) will be mapped to this
coordinate set. The numeric format assumed
is 12-bit unsigned binary integer.
UMAX,
VMAX,
WMAX
The memory addresses of the target image
boundaries corresponding to the bottom,
right side, and last page of the image being
generated are defined in all devices by the
parameters UMAX, VMAX, and WMAX,
respectively. These values should be greater
than the UMIN/VMIN/WMIN values defined
above. Numeric format assumed is unsigned
12-bit binary integer.
Note: The parameter UMAX must exceed UMIN so as to
ensure that a minimum of 5 system clock cycles in two-
dimensional operation, or 15 clock cycles in three-dimen-
sional operation, pass between the periods in which these
two target address values are generated. Thus in 2D nearest
neighbor operation UMAX must be 5 greater than UMIN. In
2D bilinear interpolation mode (4-pixel two-dimensional
kernel) the distance must be two pixels in the target image
(actually enforcing a spacing of 8 system clocks).
UMINI,
VMINI,
WMINI
UMAXI,
VMAXI,
WMAXI
The target image addresses corresponding to
those of the top, left side, and front page of the
2 or 3 dimensional region indicated by the
valid target address flag TVAL are UMINI,
VMINI, and WMINI, respectively. Thus, to
define a valid region beginning at “m,” the
MINI parameter value is “m,” These parame-
ters are assumed to be in 12-bit unsigned
binary integer format. Proper TVAL operation
requires UMIN < UMINI < UMAXI
< UMAX, etc.
The target image addresses one more than
those of the right side, bottom and back page
of the region indicated by the valid target
address flag TVAL are UMAXI, VMAXI, and
WMAXI, respectively. Thus, to define a valid
region ending at “n,” the MAXI parameter
value is “n+1”. These parameters are assumed
to be in 12-bit unsigned integer format.
11
11 Page | ||
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| PDF Descargar | [ Datasheet TMC2302AKEC1.PDF ] | |
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