PDF TMC2193 Data sheet ( Hoja de datos )

Número de pieza	TMC2193
Descripción	10 Bit Encoder
Fabricantes	Fairchild Semiconductor
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TMC2193 10 Bit Encoder www.fairchildsemi.com Features • Multiple input formats – 24 bit RGB – 20 bit CCIR601 – 10 bit CCIR656 – 10 bit Digital Composite • Synchronization modes – Master – Slave – Genlock – CCIR656 • Subcarrier modes – Free-run – Subcarrier reset – Genlock – DRS-lock • Ancillary Data Control (ANC) • Pixel rates from 10 MHz to 15 MHz • Programmable horizontal timing • Programmable vertical blanking interval (VBI) • Line-by-line pedestal enable • Programmable pedestal height from -20 IRE to 20 IRE • Programmable burst amplitude and phase • Controlled edge rates for – Sync – Burst – Active video • Programmable color space matrix • 8:8:8 video reconstruction • Four 10 bit D/A’s with independent trim • Individual power down modes for each D/A • Multiple output formats – RGB – Y PB PR – Betacam – S-video – Composite – Digital composite output • Pin-driven and data-driven, window keying • Closed Caption waveform generation (13.5 MHz only) • Sin(X)/X compensation ﬁlter • 5 bit VBI line counter • 3 bit ﬁeld counter • Internal test pattern generation – 100% Color Bars – 75% Color Bars – Modulated Ramp Applications • Broadcast Television • Nonlinear Video Processing Block Diagram PD[23:0] PRE- PROCESSOR OL[4:0] KEY gr/y bl/cb OVERLAY rd/cr MIXER Gr/Y Bl/Pb Rd/Pr SYNC INSERT COLOR SPACE MATRIX U V CHROMA PROCESSOR CVBS[9:0] Y CC SYNC INSERT FVHGEN MPU sync/mid Gr/Y Comp Bl/Pb Y Rd/Pr Ch KEY MIX INTERP. INTERP. INTERP. COMP2 INTERP. REFDAC CBYP1 DAC1 RREF1 CBYP2 DAC2 RREF2 CBYP3 DAC3 RREF3 CBYP4 DAC4 RREF4 DAC REF. 65-6294-01 REV. 1.0 3/26/03 1 page PRODUCT SPECIFICATION TMC2193 Pin Deﬁnitions (continued) Pin Name PXCK Pin Number 95 Value TTL RESET 94 TTL VSIN 55 TTL SYNC & CONTROL OUTPUTS (11 pins) FLD[2:0] 81–83 TTL HSOUT 74 TTL LINE[4:0] 76–80 TTL PDC 73 TTL Description Pixel Clock Input. PXCK is a clock signal that period is twice the sample rate of the pixel data. The operating range is 20 to 30 MHz. The clock is internally divided by 2 to generate the internal pixel clock, PCK. PXCK drives the entire TMC2193 except the asynchronous microprocessor interface. Master Chip Reset. When LOW, All outputs are tri-stated and the internal state machines and control registers are reset. At rising edge of RESET, all outputs are active, the preset values will be loaded into the control registers and the internal states machines start to operate. Vertical Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2193 will start a new vertical field with each falling edge of VSIN that is coincident with HSIN. Field Identifier. Field Identifier outputs the current field number. For all video standards the field identifier will cycle through the eight counts. Horizontal Sync Output. The alignment of HSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. Vertical Blanking Interval Line Identifier. LINE identifies the current line number for the first 31 lines. If the line count is greater than 31 then LINE is 11111b. The first line with a vertical serration is considered to be line 0. Pixel Data Control. When PDCDIR = LOW: At a rising edge, The next pixel starts a controlled ramp of the PD data. At a falling edge, the pixel prior is the last PD used in the ramp. The rising edge is determined by the PDCCNT control register, the falling edge of PDC is determined by the horizontal timing registers. VSOUT 75 TTL DATA INPUTS (39 pins) CVBS[9:0] 84–93 TTL OL[4:0] 21–25 TTL PD[23:0] 27–38, 41–52 TTL ANALOG INTERFACE – Video Out (5 pins) Ref. DAC 19 0.675Vp-p DAC1 15 1.35Vp-p DAC2 10 1.35Vp-p DAC3 5 1.35Vp-p DAC4 2 1.35Vp-p When PDCDIR = HIGH: PDCIN is used to override the internal PDC. When HIGH, the internal PDC controls the blank and unblank window. When LOW, the video remains blanked regardless of the internal PDC. All edges have the same ramp control as the internal PDC. Vertical Sync Output. The alignment of VSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. Composite Data Input Overlay Control Component Data Input Selectable sync only or midpoint reference D/A Composite or Green D/A Luma or Blue D/A Chroma or Red D/A Composite D/A with optional keying REV. 1.0 3/26/03 5 5 Page PRODUCT SPECIFICATION TMC2193 Table 2. Expected Output Values for the CSM with YCBCR Inputs Color White Yellow Cyan Green Magenta Red Blue Black Blank Pedestal Sync Inputs 5:2 Outputs 7:3 Outputs Y CB CR Y U V Y U V Y PB PR G B R 876 0 0 536 0 0 568 0 0 568 0 0 568 568 568 776 -448 73 475 -235 54 503 -249 57 514 -284 46 568 0 568 614 151 448 376 79 -332 407 84 -351 407 96 -284 568 568 0 514 -297 -375 315 -156 -278 340 -165 -294 340 -189 -238 568 0 0 362 297 375 222 156 278 240 165 294 240 189 238 0 568 568 262 -151 448 160 -79 332 173 -84 351 173 -96 284 0 0 568 100 448 -73 61 235 -54 66 249 -57 66 284 -46 0 568 0 000000000000000 64 240 256 256 256 256 256 44 0 0 8 12 12 12 Table 3. Expected Output Values for the CSM with RGB Inputs Inputs 5:2 Outputs 7:3 Outputs Color G B R Y U V Y U V Y PB PR G B R White 1020 1020 1020 536 0 0 568 0 0 568 0 0 568 568 568 Yellow 1020 0 1020 475 -235 54 503 -249 57 514 -284 46 568 0 568 Cyan 1020 1020 0 376 79 -332 407 84 -351 407 96 -284 568 568 0 Green 1020 0 0 315 -156 -278 340 -165 -294 340 -189 -238 568 0 0 Magenta 0 1020 1020 222 156 278 240 165 294 240 189 238 0 568 568 Red 0 0 1020 160 -79 332 173 -84 351 173 -96 284 0 0 568 Blue 0 1020 0 61 235 -54 66 249 -57 66 284 -46 0 568 0 Black 000000000000000 Table 4. Coefﬁcient sets YCBCR inputs YPBPR outputs RGB Outputs NTSC NTSC NTSC NTSC -EIA -M PAL-I -EIA -M PAL-I MCF1 54C 4E5 530 54C 4E5 530 MCF2 000 000 000 E34 E57 E3D MCF3 000 000 000 C4E C96 C62 MCF4 48b 433 473 48B 433 473 MCF5 000 000 000 92D 87B 8FC MCF6 668 5EC 646 668 5EC 646 MCF7 000 000 000 742 6B5 71C MCF8 54C 54C 54C 800 8A8 800 MCF9 514 514 514 800 8A8 800 MCF10 514 514 514 800 8A8 800 Table 5. Coefﬁcient sets YCBCR inputs YPBPR outputs RGB Outputs NTSC NTSC NTSC NTSC -EIA -M PAL-I -EIA -M PAL-I MCF1 2AC 278 29E 2AC 278 29E MCF2 085 07B 082 085 07B 082 MCF3 15C 142 155 15C 142 155 MCF4 240 215 234 240 215 234 MCF5 C09 C09 C09 C09 C09 C09 MCF6 404 3B7 3EF 404 3B7 3EF MCF7 8F2 8F2 8F2 8F2 8F2 8F2 MCF8 800 8A8 800 48D 48D 474 MCF9 8F2 9AB 920 48D 48D 474 MCF10 654 6D8 679 48D 48D 474 REV. 1.0 3/26/03 11 11 Page

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