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PDF TP3420A Data sheet ( Hoja de datos )
| Número de pieza | TP3420A | |
| Descripción | ISDN S/T Interface Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
July 1994
TP3420A
ISDN S/T Interface Device
General Description
The TP3420A is an enhanced version of the TP3420, with a
number of upgraded features for compliance with the new
release of ANSI T1.605-1991 and CCITT I-430. At initial
power-up the device is fully backwards compatible with the
TP3420 device, and modifications to the firmware are only
required to take advantage of the new features.
The TP3420A S Interface Device (SID™) is a complete
monolithic transceiver for data transmission on twisted pair
subscriber loops. It is built on National’s advanced 1.0 mi-
cron double-metal CMOS process, and requires only a
single +5V supply. All functions specified in CCITT recom-
mendation I.430 (1991) and ANSI T1.605 (1991) for ISDN
basic access at the “S” and “T” interfaces are provided, and
the device can be configured to operate either in a TE (Ter-
minal Equipment), in an NT-1 or NT-2 (Network Termination)
or as a PABX line-card or trunk-card device.
As specified in I.430, full-duplex transmission at 192 kb/s is
provided on separate transmit and receive twisted wire pairs
using inverted Alternate Mark Inversion (AMI) line coding. 2
“B” channels, each of 64 kb/s, and 1 “D” channel at 16 kb/s
are available for users’ data. In addition, the TP3420A pro-
vides the 800 b/s “S1”, “S2” & “Q” multiframe channels for
Layer 1 maintenance.
All I.430 wiring configurations are supported by the TP3420A
SID, including the “passive bus” for up to 8 TE’s distributed
within 200 meters of low capacitance cable, and
point-to-point and point-to-star connections up to at least
1500 meters (24AWG). Adaptive receive signal processing
ensures low bit error rates on any of the standard types of
cable pairs commonly found in premise wiring installations
when tested with the noise sources specified in I.430.
Features
n 2 B + D 4-wire 192 kb/s transceiver
n Selectable TE or NT mode
n Exceeds I.430 range: 1.5 km point-to-point
n Adaptive receiver for high noise immunity
n Adaptive and fixed timing options for NT-1
n Clock resynchronizer and elastic buffers for NT-2/LT
n Slave-slave mode for NT-2 trunks
n Extensive hardware support for SC1, SC2 and Q
channel messaging
n Bipolar violation detection and FECV messaging
n Selectable system interface formats
n MICROWIRE™ and SCP compatible serial control
interface
n TP3054/7 Codec/Filter COMBO™ compatibility
n Single +5V supply
n 20-pin package DIP, PLCC
Applications
n Same Device for NT, TE and PBX Line Card
n Point-to-Point Range Extended to 1.5 km
n Point-to-Multipoint for all I.430 Configurations
n Easy Interface to:
LAPD Processor MC68302, HPC16400
Terminal Adapter MC68302, HPC16400
Codec/Filter COMBO TP3054/7 and TP3076
“U” Interface Device TP3410
Line Card Backplanes — No External PLL Needed
n Line Monitor Mode for Test Equipment
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
COMBO™, MICROWIRE™ and SID™ are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS009143
www.national.com
1 page  
Functional Description (Continued)
boundary, by using a 0+ bit followed by a 0− balance bit to in-
dicate the start of a frame, and forcing the first binary zero
following the balance bit to be of the same polarity as the bal-
ance bit.
In the Network Termination (NT) to the Terminal Equipment
(TE) transmission direction the frame contains an echo
channel, the E bit, which is used to retransmit the D bits that
are received from the TE. The last bit of this frame is used as
a frame balancing bit. In the TE to NT direction,
d.c.-balancing is carried out for each channel, as illustrated
in Figure 2.
LINE TRANSMIT SECTION
The differential line-driver outputs, Lo+ and Lo−, are de-
signed to drive a transformer with an external termination re-
sistor. A suitable 2:1 transformer, terminated in 50Ω, results
in a signal amplitude of nominally 750 mV pk on the line
which fully complies with the I.430 pulse mask specifica-
tions. When driving a binary 1 symbol the output presents a
high impedance in accordance with I.430. When driving a 0+
or 0− symbol a voltage-limited current source is turned on.
Short-circuit protection is included in the output stage;
over-voltage protection is required externally, see the Appli-
cations section.
LINE RECEIVE SECTION
The receive input signal should be derived via a 1:1 trans-
former, or a 1:2 transformer of the same type used for the
transmit direction. At the front-end of the receive section is a
continuous filter which limits the noise bandwidth. To correct
pulse attenuation and distortion caused by the transmission
line in point-to-point and extended passive bus applications,
an adaptive equalizer enhances the received pulse shape,
thereby restoring a “flat” channel response with maximum
eye opening over a wide spread of cable attenuation charac-
teristics. This equalizer is always enabled when either TE
mode or NT Mode Adaptive Sampling is selected, but is dis-
abled for short passive bus applications when NT Mode
Fixed Sampling is selected. An adaptive threshold circuit
maximizes the Signal-to-Noise ratio in the eye at the detec-
tor for all loop conditions.
In NTF mode the receive baud sampling point is fixed rela-
tive to the transmit baud clock. This ensures accurate sam-
pling of received pulses with differential delays on a passive
bus, thus extending the short passive bus range to over
250m of low capacitive cable.
In NTA and TE modes, the receive baud sampling is adap-
tive. In these modes, a DPLL (Digital Phase-Locked Loop)
recovers a low-jitter clock for optimum sampling of the re-
ceived symbols. The MCLK input provides the reference
clock for the DPLL at 15.36 MHz. Clocks for the digital inter-
face timing may either be derived from this recovered clock,
as in TE mode Digital System Interface Master, or may be
slaved to an external source, as in the T-interface side of an
NT-2 (TES mode). In TES and NT modes, re-timing circuitry
on the TP3420A allows the MCLK frequency to be plesio-
chronous (i.e., free-running) with respect to the network
clock, i.e. the 8 kHz FSa input. With a tolerance on the MCLK
oscillator of 15.36 MHz ±100 ppm, the lock-in range of the
DPLL allows the network clock frequency to deviate up to
±50 ppm from nominal.
When the device is powered-down (either on initial
powering-on of the device or after using a PDN command), a
Line-Signal Detect circuit is enabled to detect the presence
of incoming data if the far-end starts to activate the loop. The
LSD circuit is disabled by a Power-Up (PUP) command.
FIGURE 1. Inverted AMI Line-Coding Rule
DS009143-4
5 www.national.com
5 Page 
Functional Description (Continued)
TABLE 4. Control Register Functions (Continued)
Function
Mnemonic
Bit Number
76543210
D Channel Access
D Channel Request, Class 1 Message
DREQ1
00001110
D Channel Request, Class 2 Message
DREQ2
00001111
D Channel Access Control
Enable D-Channel Access Mechanism, TE Mode (Note 8) DACCE
10010000
Disable D-Channel Access Mechanism, TE Mode (Note 8) DACCD
10010001
Force Echo Bit to 0
EBIT0
10010110
Force Echo Bit to Inverted Received D Bit
EBITI
10010111
Reset EBITI and EBIT0 to Normal Condition (Note 6)
EBITNRM 1 0 0 1 1 1 0 0
D Channel Clock Enable
DCKE
11110001
End of Message Interrupt
EOM Interrupt Enabled (Note 6)
EIE 0 0 0 1 0 0 0 0
EOM Interrupt Disabled
EID 0 0 0 1 0 0 0 1
Multiframe Circuit and Interrupt
Enable SC1/Q Messaging and MFR1 Interrupt
MIE1
00010010
Disable SC1/Q Message and Interrupt (Note 6)
MID1
00010011
Enable 5 ms Interrupt (Every Multiframe)
MFC1E
00100010
Disable 5 ms Interrupt (Note 6)
MFC1D
00100011
Enable 30 ms Interrupt (6 Multiframes)
MFC6E
00100100
Disable 30 ms Interrupt (Note 6)
MFC6D
00100101
Enable SC2 Messaging and MFR2 Interrupt
MIE2
00100110
Disable SC2 Messaging and Interrupt (Note 6)
MID2
00100111
Multiframe Receive Message Validation
Enable 3x and 1x Validation of Received Data
ENV
00101000
Disable 3x and 1x Validation of Received Data (Note 6)
DISV
00101001
Multiframe Transmit Registers
Write to Multiframe Transmit Register
MFT1L
0 0 1 1 M1 M2 M3 M4
(SC1/Q Low Priority Messages)
Write to Multiframe Transmit Register
MFT1H
0 1 0 0 M1 M2 M3 M4
(SC1/Q High Priority Messages)
Write to Multiframe Transmit Register
MFT2
0 1 0 1 M1 M2 M3 M4
(SC2 Messages)
B1 Channel Enable/Disable
B1 Channel Enabled
B1E 0 0 0 1 0 1 0 0
B1 Channel Disabled (Note 6)
B1D
00010101
B2 Channel Enable/Disable
B2 Channel Enabled
B2E 0 0 0 1 0 1 1 0
B2 Channel Disabled (Note 6)
B2D
00010111
Loopback Test Modes
Loopback B1 Towards Line Interface
LBL1
00011000
Loopback B2 Towards Line Interface
LBL2
00011001
Loopback 2B+D Towards Digital Interface
LBS 0 0 0 1 1 0 1 0
Loopback B1 Towards Digital Interface
LBB1
00011100
Loopback B2 Towards Digital Interface
LBB2
00011101
Clear All Loopbacks (Note 6)
CAL
00011011
Control Device State Reading
Enable the Device State Output on the NOCST
ENST
10010010
11 www.national.com
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| PDF Descargar | [ Datasheet TP3420A.PDF ] | |
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