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PDF TP3155V Data sheet ( Hoja de datos )
| Número de pieza | TP3155V | |
| Descripción | TP3155 Time Slot Assignment Circuit | |
| Fabricantes | National Semiconductor | |
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September 1993
TP3155 Time Slot Assignment Circuit
General Description
The TP3155 is a monolithic CMOS logic circuit designed to
generate transmit and receive frame synchronization pulses
for up to 8 COMBOTM CODEC Filters Each frame sync
pulse may be independently assigned to a time slot in a
frame of up to 32 time slots Assignments are controlled by
loading in an 8-bit word via a simple serial interface port
This control interface is compatible with that used on the
TP3020 TP3021 and 2910 2911 CODECs enabling an
easy upgrade to COMBO CODEC Filters to be made
Features
Y Controls up to 8 COMBO CODEC Filters
Y Independent transmit and receive time slot assignments
Y 8-channel unidirectional mode
Y Up to 32 time slots per frame
Y Serial control interface compatible with TP3020 TP3021
CODECs
Y LS TTL and CMOS compatible inputs
Y 5 mW 5V operation
Typical Application
TRI-STATE is a registered trademarks of National Semiconductor Corp
COMBOTM is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL H 5118
TL H 5118 – 1
RRD-B30M115 Printed in U S A
1 page  
Functional Description
OPERATING MODES
The TP3155 control interface requires an 8-bit serial control
word which is compatible with the TP3020 TP3021 and
2910 2911 CODECs Two bits X and R define which of the
two groups of frame sync outputs FSX0 to FSX3 or FSR0 to
FSR3 is affected by the control word and a 6-bit assign-
ment field specifies the selected time slot from 0 to 31 A
frame sync output is active-high for one time slot which is
always 8 cycles of BCLK A frame may consist of any num-
ber of time slots up to 32 If a timeslot is assigned which is
beyond the number of time slots in a frame the FSX or FSR
output to which it was assigned will remain inactive
Two modes of operation are available Mode 1 is for sys-
tems requiring different time slot assignments for the trans-
mit and receive direction of each channel Mode 1 is select-
ed by leaving pin 9 (MODE) open-circuit or connecting it to
VCC In this case Pin 13 is the RSYNC input which defines
the start of each receive frame and the four outputs
FSR0 – FSR3 are assigned with respect to RSYNC The
XSYNC input defines the start of each transmit frame and
outputs FSX0 – FSX3 are assigned with respect to XSYNC
XSYNC may have any phase relationship with RSYNC In-
puts CH0 and CH1 select the channel from 0 to 3 (see
Table Ia)
Mode 2 provides the option of assigning all 8 frame sync
outputs with respect to the XSYNC input Mode 2 is select-
ed by connecting pin 9 (MODE) to GND This makes the
TP3155 TSAC useful for either an 8-channel undirectional
controller or for systems in which the transmit and receive
directions of each channel are always assigned to the same
time slot as the other i e the FSX and FSR inputs on the
COMBO CODEC Filter are hard-wired together In this
case logical selection of the channel to be assigned is
made via inputs CH0 CH1 and CH2 (see Table Ib)
POWER-UP INITIALIZATION
During power-up all frame sync outputs FSX0 – FSX3 and
FSR0 – FSR3 are inhibited and held low No outputs will go
active until a valid time slot assignment is made
LOADING CONTROL DATA
During the loading of control data the binary code for the
selected channel must be set on inputs CH0 and CH1 (and
CH2 in mode 2) see Tables Ia and Ib
Control data is clocked into the DC input on the falling
edges of CLKC while CS is low
A new time slot assignment is transferred to the selected
assignment register on the high going transition of CS The
new assignment is re-synchronized to the system clock
such that the new FS output pulses will start at the next
complete valid time slot after the rising edge of CS
TIME SLOT COUNTER OPERATION
At the start of TS0 of each transmit frame defined by the
first falling edge of BCLK after XSYNC goes high the trans-
mit time slot counter is reset to 000000 and begins to incre-
ment once every 8 cycles of BCLK Each count is compared
with the 4 transmit assignment registers and on finding a
match a frame sync pulse is generated at that FSX output
Similarly the first falling edge of BCLK after RSYNC goes
high defines the start of receive TS0 and outputs
FSR0 – FSR3 are generated with respect to TS0 when the
receive time slot counter matches the appropriate receive
assignment register
TSX OUTPUT
In mode 1 (separate transmit and receive assignments) this
output pulls low whenever any FSX output pulse is being
generated In mode 2 this output pulls low whenever any
FSX or FSR output is being generated At all other times it is
open-circuit allowing the TSX outputs of a number of
TSACS to be wire-ANDed together with a common pull-up
resistor This signal can be used to control the TRI-STATE
enable input of a line driver to buffer the transmit PCM bus
from the CODEC Filters to the backplane
TABLE Ia Control Mode 1
(TP3020 TP3021 Compatible)
X R T5 T4 T3 T2 T1 T0
X is the first bit clocked into the DC input
Control Data Format
T5 T4 T3 T2 T1 T0 Time Slot
000000
000001
000010
0
1
2
011110
30
011111
31
1 X X X X X (Note 1)
CH1
0
0
1
1
CH0
0
1
0
1
Channel Selected
Assign to FSx0 and or FSR0
Assign to FSx1 and or FSR1
Assign to FSx2 and or FSR2
Assign to FSx3 and or FSR3
XR
Action
0 0 Assign time slot to both selected FSX and FSR
0 1 Assign time slot to selected FSX only
1 0 Assign time slot to selected FSR only
1 1 Disable both selected FSX and FSR
CH2
0
0
0
0
1
1
1
1
TABLE Ib Control Mode 2
CH1 CH0 Channel Selected
0 0 Assign to FSX0
0 1 Assign to FSX1
1 0 Assign to FSX2
1 1 Assign to FSX3
0 0 Assign to FSR0
0 1 Assign to FSR1
1 0 Assign to FSR2
1 1 Assign to FSR3
XR
Action
00
(0 1
10
Assign time slot to selected output
11
Disable selected output
Note 1 When T5 e 1 then the appropriate FSX or FSR output is inactive
5
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