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PDF TP3076J Data sheet ( Hoja de datos )
| Número de pieza | TP3076J | |
| Descripción | COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 1994
TP3076
COMBO® II Programmable PCM CODEC/Filter for ISDN
and Digital Phone Applications
General Description
The TP3076 is a second-generation combined PCM CODEC
and Filter devices optimized for digital switching applications
on subscriber line and trunk cards and digital phone applica-
tions. Using advanced switched capacitor techniques,
COMBO II combines transmit bandpass and receive low-
pass channel filters with a companding PCM encoder and
decoder. The devices are A-law and µ-law selectable and
employ a conventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programmable func-
tions may be controlled via a serial control port.
Channel gains are programmable over a 25.4 dB range in
each direction.
To enable COMBO II to interface to the SLIC control leads, a
number of programmable latches are included; each may be
configured as either an input or an output. The TP3076 pro-
vides 4 latches.
Features
n Complete CODEC and Filter system including:
— Transmit and receive PCM channel filters
— µ-law or A-law companding coder and decoder
— Receive power amplifier drives 300Ω
— 4.096 MHz serial PCM data (max)
n Programmable functions:
— Transmit gain: 25.4 dB range, 0.1 dB steps
— Receive gain: 25.4 dB range, 0.1 dB steps
— Time-slot assignment; to 64 slots/frame
— 4 interface latches
— A or µ-law
— Analog loopback
— Digital loopback
n Direct interface to solid-state SLICs
n Standard serial control interface
n 80 mW operating power (typ)
n 1.5 mW standby power (typ)
n Designed for CCITT and LSSGR specifications
n TTL and CMOS compatible digital interfaces
Note: See also AN-614 COMBO II application guide.
Block Diagram
FIGURE 1.
TRI-STATE® and COMBO® are registered trademarks of National Semiconductor Corporation.
MICROWIRE/PLUS™ is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS009758
DS009758-1
www.national.com
1 page  
Programmable Functions (Continued)
Coding Law Selection
Bits “MA” and “IA” in Table 2 permit the selection of µ255
coding or A-law coding, with or without even bit inversion.
Analog Loopback
Analog Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2. In the
analog loopback mode, the Transmit input VFXI is isolated
from the input pin and internally connected to the VFRO out-
put, forming a loop from the Receive PCM Register back to
the Transmit PCM Register. The VFRO pin remains active,
and the programmed settings of the Transmit and Receive
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Digital Loopback
Digital Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2. This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at DX1. PCM de-
coding continues and analog output appears at VFR0. The
output can be disabled by programming ‘No Output’ in the
Receive Gain Register (see Table 8).
INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro-
grammed as a logic input or output by writing the appropriate
instruction to the LDR, see Table 1 and Table 3. For mini-
mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3076, bits 2 and 3 should
always be programmed as “1” (outputs).
Bits L3–L0 must be set by writing the specific instruction to
the LDR with the L bits in the second byte set as follows:
TABLE 3. Byte 2 Functions of Latch Direction Register
Byte 2 Bit Number
76543210
L0 L1 L2 L3
Ln Bit
0
1 1XX
IL Direction
Input
1 Output
X = Don’t Care
INTERFACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (ILR) as shown in
Table 1 and Table 4. Latches configured as inputs will sense
the state applied by an external source, such as the
Off-Hook detect output of a SLIC. All bits of the ILR, i.e.
sensed inputs and the programmed state of outputs, can be
read back in the 2nd byte of a READ from the ILR.
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first
followed immediately by the Latch Direction Register.
TABLE 4. Interface Latch Data Bit Order
Bit Number
765432
D0 D1 D2 D3 D4 D5
1
X
0
X
VIN = +Full Scale
VIN = 0V
VIN = −Full Scale
TABLE 5. Coding Law Conventions
µ255 Law
MSB LSB
10000000
11111111
11111111
00000000
True A-Law with
Even Bit Inversion
MSB LSB
10101010
11010101
01010101
00101010
A-Law without
Even Bit Inversion
MSB LSB
111111111
100000000
000000000
011111111
Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.
5 www.national.com
5 Page 
Timing Specifications (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for
+70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits
VCC = +5V ±5%; VBB = −5V ±5%; TA = 0˚C to
are assured by correlation with other production
tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V,
TA = 25˚C.
All timing parameters are measured at VOH = 2.0V and VOL = 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min Typ Max Units
PCM INTERFACE TIMING
High to Data Valid
Applies if FSX/R Rises Later Than
BCLK Rising Edge in Non-Delayed Data
80 ns
Mode Only
tSDB
Setup Time, DR1
Valid to BCLK Low
30 ns
tHBD
Hold Time, BCLK
Low to DR1 Invalid
SERIAL CONTROL PORT TIMING
15 ns
fCCLK
tWCH
tWCL
tRC
tFC
tHCS
Frequency of CCLK
Period of CCLK High
Period of CCLK Low
Rise Time of CCLK
Fall Time of CCLK
Hold Time, CCLK Low
to CS Low
Measured from VIH to VIH
Measured from VIL to VIH
Measured from VIL to VIH
Measured of VIH to VIL
CCLK1
2048 kHz
160 ns
160 ns
50 ns
50 ns
10 ns
tHSC
Hold Time, CCLK
Low to CS High
CCLK8
100 ns
tSSC
Setup Time, CS
Transition to CCLK Low
60 ns
tSSC0
Setup Time, CS
Transition to CCLK High
To Insure CO is Not Enabled
for Single Byte
60
ns
tSDC
Setup Time, CI
Data In to CCLK Low
50 ns
tHCD
Hold Time, CCLK
Low to CO Invalid
50 ns
tDCD
Delay Time, CCLK High
to CO Data Out Valid
Load = 100 pF Plus 2 LSTTL Loads
80 ns
tDSD
Delay Time, CS Low
to CO Valid
Applies Only if Separate
CS Used for Byte 2
80 ns
tDDZ
Delay Time, CS or 9th CCLK
High to CO High Impedance
Applies to Earlier of CS
High or 9th CCLK High
15 80 ns
INTERFACE LATCH TIMING
tSLC Setup Time, IL to
CCLK 8 of Byte 1
Interface Latch Inputs Only
100
ns
tHCL Hold Tme, IL Valid from
8th CCLK Low (Byte 1)
50 ns
tDCL
Delay Time CCLK8 of
Byte 2 to IL
Interface Latch Outputs Only
CL = 50 pF
Note 14: Applies only to MCLK Frequencies ≥ 1.536 MHz. At 512 kHz a 50:50 ±2% Duty Cycle must be used.
200 ns
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