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PDF TP2640 Data sheet ( Hoja de datos )
| Número de pieza | TP2640 | |
| Descripción | P-Channel Enhancement-Mode Vertical DMOS FETs | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
TP2640
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
General Description
►► Low threshold (-2.0V max.)
►► High input impedance
►► Low input capacitance
►► Fast switching speeds
►► Low on-resistance
►► Free from secondary breakdown
►► Low input and output leakage
Applications
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
►► Logic level interfaces - ideal for TTL and CMOS
►► Solid state relays
►► Battery operated systems
►► Photo voltaic drives
►► Analog switches
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
►► General purpose line drivers
►► Telecom switches
Ordering Information
Part Number
Package
Option
TP2640LG-G
8-Lead SOIC
TP2640N3-G
3-Lead TO-92
Packing
2500/Reel
1000/Bag
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
-400V
15Ω
ID(ON)
(min)
-2.0A
VGS(th)
(max)
-0.7V
TP2640N3-G P002
TP2640N3-G P003
Pin Configuration
TP2640N3-G P005
3-Lead TO-92 2000/Reel
TP2640N3-G P013
TP2640N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
DRAIN
DRAIN
DRAIN
DRAIN
GATE
SOURCE
N/C
N/C
8-Lead SOIC
SOURCE
DRAIN
GATE
TO-92
Product Marking
YYWW
P2640
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC
Typical Thermal Resistance
Package
θja
8-Lead SOIC
101OC/W
TO-92
132OC/W
SiTP
2640
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92
Doc.# DSFP-TP2640
B081613
Supertex inc.
www.supertex.com
1 page  
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
D θ1
8
TP2640
Note 1
(Index Area
D/2 x E1/2)
E1 E
L2 Gauge
Plane
1
Top View
A A2
A1
A
Seating
Plane
eb
Side View
A
Note 1
h
L
L1
θ
View B
h
Seating
Plane
View B
View A-A
Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
A A1 A2 b D E E1 e h L L1 L2 θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
0.25 0.40
0O 5O
Dimension
(mm)
NOM
-
-
-
-
4.90
6.00
3.90
1.27
BSC
-
-
1.04 0.25
REF BSC
-
-
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00*
0.50 1.27
8O 15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
Doc.# DSFP-TP2640
B081613
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet TP2640.PDF ] | |
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