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PDF TP2104 Data sheet ( Hoja de datos )
| Número de pieza | TP2104 | |
| Descripción | P-Channel Enhancement-Mode Vertical DMOS FETs | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TP2104 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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Supertex inc.
TP2104
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
►► High input impedance and high gain
►► Low power drive requirement
►► Ease of paralleling
►► Low CISS and fast switching speeds
►► Excellent thermal stability
►► Integral source-drain diode
►► Free from secondary breakdown
Applications
►► Logic level interfaces - ideal for TTL and CMOS
►► Solid state relays
►► Analog switches
►► Power management
►► Telecom switches
General Description
This low threshold, enhancement-mode (normally-off) transistor
utilizes a vertical DMOS structure and Supertex’s well-
proven, silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of
bipolar transistors and the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic
of all MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Part Number
Package Option
Packing
TP2104K1-G
TO-236AB (SOT-23)
TP2104N3-G
3-Lead TO-92
TP2104N3-G P002
TP2104N3-G P003
TP2104N3-G P005 3-Lead TO-92
TP2104N3-G P013
TP2104N3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
3000/Reel
1000/Bag
2000/Reel
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Typical Thermal Resistance
Package
θja
TO-236AB (SOT-23)
203OC/W
TO-92
132OC/W
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
-40V
6.0Ω
Pin Configuration
VGS(th)
(max)
-2.0V
DRAIN
SOURCE
GATE
TO-236AB (SOT-23)
SOURCE
DRAIN
GATE
TO-92
Product Marking
P1LW
W = Code for week sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-236AB (SOT-23)
SiTP YY = Year Sealed
2 1 0 4 WW = Week Sealed
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92
Doc.# DSFP-TP2104
B081313
Supertex inc.
www.supertex.com
1 page  
3-Lead TO-236AB (SOT-23) Package Outline (K1)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
TP2104
E1 E
12
e
e1
Top View
A A2
A1
Side View
b
A
Seating
Plane
A
0.25
Gauge
Plane
L
L1
View B
Seating
Plane
View B
View A - A
Symbol
A A1 A2 b
MIN 0.89 0.01 0.88 0.30
Dimension
(mm)
NOM
-
- 0.95 -
MAX 1.12 0.10 1.02 0.50
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO236ABK1, Version C041309.
D
2.80
2.90
3.04
E
2.10
-
2.64
E1
1.20
1.30
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20†
0.50
0.60
L1
0.54
REF
θ
0O
-
8O
Doc.# DSFP-TP2104
B081313
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet TP2104.PDF ] | |
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