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PDF TS68HC901 Data sheet ( Hoja de datos )
| Número de pieza | TS68HC901 | |
| Descripción | HCMOS MULTI-FUNCTION PERIPHERAL | |
| Fabricantes | STMicroelectronics | |
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® TS68HC901
HCMOS MULTI-FUNCTION PERIPHERAL
The TS68HC901 CMFP (CMOS Multi-Function
Peripheral) is a combination of many of the neces-
sary peripheral functions in a microprocessor sys-
.tem.
Included are :
8 INPUT/OUTPUT PINS
• Individually programmable direction
. • Individual interrupt source capability
- Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
• 8 Internal sources
• 8 External sources
• Individual source enable
• Individual source masking
• Programmable interrupt service modes
- Polling
- Vector generation
. - Optional In-service status
• Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY
PROGRAMMABLE PRESCALING
• Two multimode timers
- Delay mode
- Pulse width measurement mode
- Event counter mode
• Two delay mode timers
. • Independent clock input
• Time out output option
SINGLE CHANNEL USART
• Full Duplex
• Asynchronous to 65 kbps
• Byte synchronous to 1 Mbps
• Internal/External baud rate generation
• DMA handshake signals
. • Modem control
• Loop back mode
68000 BUS COMPATIBLE
DESCRIPTION
The use of the CMFP in a system can significantly
reduce chip count, thereby reducing system cost.
The CMFP is completely 68000 bus compatible, and
24 directly addressable internal registers provide
the necessary control and status interface to the pro-
grammer.
The CMFP is a derivative of the MK3801 STI, a Z80
family peripheral.
September 1992
48
1
PDIP48
PLCC52
(Ordering Information at the end of the Datasheet
1/42
1 page  
TS68HC901
RS1-RS5: Register Address Bus (inputs). The ad-
(A1-A5) dress bus is used to address one of the
internal registers during a read or write
cycle.
D0-D7 :
Data Bus (bi-directional, tri-stateable).
This bus is used to receive data from or
transmit data to the MFP’s internal regis-
ters during a processor read or write cy-
cle. During an interrupt acknowledge cy-
cle, the data bus is used to pass a vector
number to the processor. Since the MFP
is an 8-bit peripheral, the MFP could be
located on either the upper or lower por-
tion of the 16-bit data bus (even or odd
address). However, during an interrupt
acknowledge cycle, the vector number
passed to the processor must be located
in the low byte of the data word. As a re-
sult, D0-D7 of the MFP must be connec-
ted to the low eight bits of the processor
data bus, placing MFP registers at odd
addresses if vectored interrupt are to be
used.
CLK :
The clock input is a single-phase TTL
compatible signal used for internal ti-
ming . This input should not be gated off
at any time and must conform to mini-
mum and maximum pulse width times.
The clock is not necessarily the system
clock in frequency nor phase. When the
bus is multiplexed (MPX=1), an address
strobe signal is connected to this pin. In
the non multiplexed mode (MPX=0), this
input is connected to the system clock
when used with a 68000 processor type
or to VSS (0VDC) when used with a 6800
processor type.
RESET : Device reset. (input, active low). Reset
disables the USART receiver and trans-
mitter, stops all timers and forces the ti-
mer outputs low, disables all interrupt
channels and clears any pending inter-
rupts. The General Purpose Interrupt/I/O
lines will be placed in the tri-state input
mode. All internal registers (except the ti-
mer, USART data registers, and transmit
status register) will be cleared.
MPX : This input selects the data bus mode:
MPX = 0 : non multiplexed mode
MPX = 1 : multiplexed mode. The register
select lines RS1-RS5 and the data bus
D0-D7 are multiplexed. An address
strobe must be connected to the CLK pin.
IRQ :
IACK :
IEI :
IEO :
I0-I7 :
SO :
SI :
RC :
TC :
RR :
TR :
Interrupt Request (output, active low, o-
pen drain). This output signals the pro-
cessor that an interrupt is pending from
the CMFP. These are 16 interrupt chan-
nels that can generate an interrupt re-
quest. Clearing the interrupt pending re-
gisters (IPRA and IPRB) or clearing the
interrupt mask registers (IMRA and
IMRB) will cause IRQ to be negated. IRQ
will also be negated as the result of an in-
terrupt acknowledge cycle, unless addi-
tional interrupts are pending in the
CM FP. Ref er to paragraph INTER-
RUPTS for further information.
Interrupt Acknowledge (input, active
l ow ). IACK i s us ed t o s ignal t he
TS68HC901 that the CPU is acknow-
ledging an interrupt. CS and IACk must
not be asserted at the same time.
Interrupt Enable In (input, active low). IEI
is used to signal the TS68HC901 that no
higher priority device is requesting inter-
rupt service.
Interrupt Enable Out (output, active low).
IEO is used to signal lower priority peri-
pherals that neither the TS68HC901 nor
another higher priority peripheral is re-
questing interrupt service.
Ge neral Purpose Interrupt I/O lines.
These lines may be used as interrupt in-
puts and/or I/O lines. When used asinter-
rupt inputs, their active edge is program-
mable. A data direction register is used to
define which lines are to be Hi-Z inputs
and which lines are to be push-pull TTL
compatible outputs.
Serial Output. This is the output of the U-
SART transmitter.
Serial Input. This is the input to the U-
SART receiver.
Receiver Clock. This input controls the
serial bit rate of the USART receiver.
Transmitter Clock. This input controls the
serial bit rate of the USART transmitter.
Receiver Ready. (output, active low)
DMA output for receiver, which reflects
the status of Buffer Full in port number
15.
Transmitter Ready. (output, active low)
DMA output for transmitter, which re-
flects the status of Buffer Empty in port
number 16.
5/42
®
5 Page 
TS68HC901
DAISY-CHAINING CMFPs
As an interrupt controller, the TS68HC901 CMFP
will support eight external interrupt sources in addi-
tion to its eight internal interrupt sources. When a
system requires more than eight external interrupt
sources to be placed at the same interrupt level,
sources may be added to the prioritized structure by
daisy-chaining CMFPs. Interrupt sources are priori-
tized internally within each CMFP and the CMFPs
are prioritized by their position in the chain. Unique
vector numbers are provided for each interrupt
sources.
The IEI and IEO signals implement the daisy-chai-
ned interrupt structure. The IEI of the highest priority
CMFP is tied low and the IEO output of this device
is tied to the next highest priority CMFP’s IEI. The
IEI and IEO signals are daisy-chained in this manner
for all CMFPs in the chain, with the lowest priority
CMFP’s IEO left unconnected. A diagram of an in-
terrupt daisy-chain is shown in figure 8.
Daisy-chaining requires that all parts in the chain
have a common IACK. When the common IACK is
asserted during an interrupt acknowledge cycle, all
parts will prioritize interrupts in parallel. When the IEI
signal to a CMFP is asserted, the part may respond
to the IACK cycle if it requires interrupt service.
Otherwise, the part will assert IEO to the next lower
priority device. Thus, priority is passed down the
chain via IEI and IEO until a part which has appen-
ding interrupt is reached. The part with the pending
interrupt passes a vector number to the processor
and does not propagate IEO.
Figure 9a :
Figure 9b :
11/42
®
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