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PDF TRCV012G7 Data sheet ( Hoja de datos )
| Número de pieza | TRCV012G7 | |
| Descripción | TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier/ Clock Recovery/ 1:16 Data Demultiplexer | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
August 2000
TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s)
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Features
s TRCV012G5 supports OC-48/STM-16 data rate
s TRCV012G7 supports:
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
s Fully-integrated limiting amplifier, clock recovery,
1:16 data demultiplexer
s No reference clock required for CDR
s 2.5 Gbits/s data output and 2.5 GHz recovered
clock output available for wavelength division
multiplex (WDM) or regenerator applications
s Programmable limiting amplifier offset
s Programmable data sampling phase
s Additional CML serial data input for system
loopback
s Parity bit generation
s Analog and digital loss of signal (LOS) indicators
s Optional demultiplexer powerdown mode
conserves power
s Single 3.3 V supply
s Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
s High-speed LVPECL digital I/O
s Jitter tolerance, transfer, and generation compliant
with the following:
— Telcordia Technologies* GR-253
— ITU-T G.825
— ITU-T G.958
s Loss of signal compliant with the following:
— Telcordia Technologies GR-253
* Telcordia Technologies is a registered trademark of Bell Com-
munications Research, Inc.
Applications
s SONET/SDH line termination equipment
s SONET/SDH add/drop multiplexers
s SONET/SDH cross connects
s SONET/SDH test equipment
Description
The Lucent Technologies Microelectronics Group
TRCV012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TRCV012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TRCV012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TRCV012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the par-
allel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices contain a limiting amplifier with 30 dB
gain, a clock and data recovery PLL with high-speed
serial clock and data outputs, and a 1:16 demulti-
plexer with differential PECL data and clock outputs.
The device provides improved optical receiver perfor-
mance when used in optically amplified systems due
to a direct slice adjust input pin and a 6 ps adjust-
ment capability in the slicing decision time. Both
devices are available in either BiCMOS or in SiGe
BiCMOS technology for lower power operation.
1 page  
Preliminary Data Sheet
August 2000
TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Pin Information (continued)
Note: In Table 1, when operating the TRCV012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter-
preted as 2.48832 Gbits/s. When operating the TRCV012G7 device at the RS FEC OC-48/STM-16 rate,
2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.)
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals
Pin Symbol* Type† Level
Name/Description
30 LAINP
32 LAINN
I Analog Limiting Amplifier Inputs (2.5 Gbits/s).
ac coupling required.
50 D2G5P O
51 D2G5N
CML
Data Output (2.5 Gbits/s NRZ). 2.5 Gbits/s differential data
output.
s Pins are high impedance when END2G5N = 1.
s Pins are active but forced to differential logic low when
MUTE2G5N = 0.
122 END2G5N Iu
118 MUTE2G5N Iu
CMOS
CMOS
Enable D2G5P/N Data Outputs (Active-Low).
0 = D2G5P/N buffer enabled
1 or no connection = D2G5P/N buffer powered off
Mute D2G5P/N Data Output (Active-Low).
0 = muted
1 or no connection = normal data
53 CK2G5P
54 CK2G5N
123 ENCK2G5N
O
Iu
CML
CMOS
Recovered Clock Output (2.5 GHz). 2.5 GHz recovered differen-
tial clock output. Pins are high impedance when ENCK2G5N = 1.
Enable CK2G5P/N Clock Output (Active-Low).
0 = CK2G5P/N buffer enabled
1 or no connection = CK2G5P/N buffer powered off
41 RREF1
I Analog Resistor Reference 1. CML current bias reference resistor. (See
Table 16, page 22 for values.)
40 RREF2
I Analog Resistor Reference 2. CML bias reference resistor. Place a
1.5 kΩ resistor to VCCD.
28 VTHP
34 VTHN
I Analog Voltage Threshold Adjust Input. This input is for monitoring
purposes only and should be left open (see Figure 3 on page 10).
26 SLADJ
I Analog Slice Level Adjustment. Adjusts slice level for the limiting amp
(see Figure 3 on page 10).
119 LOSAN
O Open Drain Loss of Analog Signal (Active-Low).
25 PRG_LOSA I
Analog Programming Voltage for LOSA Threshold. Programming
voltage is scaled (see Figure 7 on page 16).
120 LOSDN
121 INLOSN
O Open Drain Loss of Digital Data (Active-Low).
Iu CMOS Input Loss of Signal (Active-Low). Forces VCO to decrease to
its minimum frequency.
0 = force VCO low
1 or no connection = normal operation
18 LFP O Analog Loop Filter PLL. Connect LFP to VCP, and LFN to VCN.
17 LFN
19 VCP
I Analog VCO Control. Connect VCP to LFP, and VCN to LFN.
16 VCN
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination
resistance of 50 Ω on this pin.
Lucent Technologies Inc.
5
5 Page 
Preliminary Data Sheet
August 2000
TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Clock and Data Recovery (CDR)
Clock Recovery Operation
The CDR circuit uses a PLL to extract the clock and retime the 2.5 Gbits/s data. The 2.5 Gbits/s data and the
2.5 GHz recovered clock are available as outputs, as well as a 155 MHz clock derived from the recovered clock.
Clock Recovery PLL Loop Filter
A typical loop filter that meets the OC-48 jitter transfer template is shown in Figure 4. Connect the filter compo-
nents and also connect LFP to VCP and connect LFN to VCN. The component values can be varied to adjust the
loop dynamic response (see Table 5).
Table 5. Clock Recovery Loop Filter Component Values
Components
C1*
C2, C3
R1
R2
Values for 2 MHz Loop Bandwidth
0.47 µF ± 10%
10 pF ± 20%
82.5 Ω ± 5%
100 kΩ ± 5%
* Capacitor C1 should be either ceramic or nonpolar.
LFP/VCP LFN/VCN
R2 C1 R1
C2 C3
Figure 4. Clock Recovery PLL Loop Filter Components
5-8061(F).a
CDR Acquisition Time
The limiting amplifier plus CDR will acquire phase/frequency lock within 10 ms after powerup and a valid SONET
signal or a 223 – 1 PRBS data signal is applied.
CDR Generated Jitter
The limiting amplifier plus CDR’s generated jitter performance meets the requirements shown in Table 6. These
specifications apply to the jitter generated at the 2.5 Gbits/s recovered clock pins (CK2G5P/N) when the following
occur: no jitter is present on the input, the limiting amplifier’s input signal is within the valid level range given in
Table 9 on page 20, and the data sequence is a valid OC-48 SONET/SDH signal.
Table 6. Clock and Data Recovery Generated Jitter Specifications
Parameter
Generated Jitter (p-p):
Measured with 12 kHz to 20 MHz Bandpass Filter
Generated Jitter (rms):
Measured with 12 kHz to 20 MHz Bandpass Filter
Typical
0.06
0.008
Max
(Device)*
0.10
0.01
Unit
UIp-p
UIrms
* This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 5 and Figure 4 is used.
Lucent Technologies Inc.
11
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| PDF Descargar | [ Datasheet TRCV012G7.PDF ] | |
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