PDF ICS854058AG Data sheet ( Hoja de datos )

Número de pieza	ICS854058AG
Descripción	DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. PRELIMINARY ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER GENERAL DESCRIPTION The ICS854058 is an 8:1 Differential-to-LVDS Clock ICS Multiplexer which can operate up to 2.5GHz and HiPerClockS™ is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS854058 has 8 selectable differential clock in- puts.The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution cir- cuits.The select pins have internal pulldown resistors.The SEL2 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 000 selects PCLK0, nPCLK0). FEATURES • High speed 8:1 differential multiplexer • 1 differential LVDS output • 8 selectable differential PCLK, nPCLK inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2.5GHz • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input • Part-to-part skew: TBD • Propagation delay: 595ps (typical) • Supply voltage range: 3.135V to 3.465V • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PCLK0 nPCLK0 PCLK1 nPCLK1 PCLK2 nPCLK2 PCLK3 nPCLK3 PCLK4 nPCLK4 PCLK5 nPCLK5 PCLK6 nPCLK6 PCLK7 nPCLK7 000 001 010 011 100 101 110 111 SEL2 SEL1 SEL0 PIN ASSIGNMENT PCLK0 1 24 PCLK7 nPCLK0 2 23 nPCLK7 PCLK1 3 22 PLCK6 nPCLK1 4 21 nPCLK6 VDD 5 20 VDD SEL0 6 19 Q0 SEL1 7 18 nQ0 SEL2 8 17 GND PCLK2 9 16 PCLK5 nPCLK2 10 15 nPCLK5 PCLK3 11 14 PCLK4 nPCLK3 12 13 nPCLK4 Q0 nQ0 ICS854058 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 854058AG www.icst.com/products/hiperclocks.html REV. A APRIL 8, 2004 1 1 page Integrated Circuit Systems, Inc. PRELIMINARY ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V ± 5% Symbol Parameter Test Conditions VOD ∆ VOD VOS ∆ VOS Differential Output Voltage V Magnitude Change OD Offset Voltage VOS Magnitude Change Minimum Typical 350 50 1.25 50 Maximum Units mV mV V mV TABLE 5. AC CHARACTERISTICS, V DD = 3.135V TO 3.465V Symbol Parameter Test Conditions Minimum Typical Maximum fMAX tPD tsk(pp) Output Frequency Propagation Delay; NOTE 1 Part-to-Part Skew; NOTE 2, 3 595 TBD 2.5 tR / tF Output Rise/Fall Time 20% to 80% 180 All parameters measured up to 1.3GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. Units GHz ps ps ps 854058AG www.icst.com/products/hiperclocks.html 5 REV. A APRIL 8, 2004 5 Page Integrated Circuit Systems, Inc. PRELIMINARY ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP 854058AG TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum Maximum N 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 www.icst.com/products/hiperclocks.html 11 REV. A APRIL 8, 2004 11 Page

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